User`s guide

Theory of Operation and Clocking
Clocking
The microprocessor address strobe (~AS) indicates that address, function
code, size, and R/~W state information is on the bus and valid. The rising
edge of ~AS is used to clock information into the logic analyzer.
On a read cycle, data must be valid for 10 ns before the rising edge of ~AS for all
logic analyzers except the HP 1660A/61A/62A, HP 16550A, and HP 16555A.
Bus Arbitration
Bus arbitration is the method used by the microprocessor and other possible
bus master devices to request, grant, and acknowledge bus ownership. The
MC68306 microprocessor provides two different ways to arbitrate the bus,
2-wire and 3-wire arbitration.
If 3-wire bus arbitration is used, the ~BGACK signal is asserted when the
microprocessor has given ownership of the bus to another device. The
inverse assembler will not attempt to interpret any data as instruction fetches
until ~BGACK is negated.
In 2-wire bus arbitration, however, ~BGACK must always be pulled high.
Signals ~BR and ~BG indicate changes in bus control, but are asynchronous
with ~AS which clocks the logic analyzer. The inverse assembler has no way
of positively determining whether the microprocessor has bus control and
instead must rely on the function code signals. Once another device assumes
bus ownership, the microprocessor tri-states the function code lines. If the
new bus master happens to drive the function codes to combinations which
are recognized as valid by the inverse assembler, then incorrect disassembly
may result.
If your microprocessor target system uses 2-wire bus arbitration, you can
work around this potential problem by synchronizing the inverse assembler
on the first state of an instruction fetch which occurs at least one or more
states after ~BG goes high.
Preprocessor Interface Hardware Reference
Theory of Operation and Clocking
3–4 MC68306 Preprocessor