Technical information

AN2317/D
Monitor Mode Signals
Low-Cost Programming and Debugging Options for M68HC08 MCUs 3
Monitor Mode Signals
The physical monitor mode interface uses up to nine connections to configure
the MCU and establish serial communications. As few as two or three
connections are used to program the MCU’s FLASH memory when the FLASH
is blank and the special “Forced Monitor Mode” is invoked. (Refer to the Monitor
ROM section of the appropriate M68HC908 data sheet.) For the purpose of this
application note, we will only consider the “normal” monitor mode interface,
which allows reprogramming. The monitor mode pin functions are discussed
here. All signal names are taken from data books or made up by the author to
identify functionality.
V
TST
/IRQ Normal monitor mode is entered after a power on reset (POR) with a high
voltage, typically called V
TST
(pronounced V test), on the MCU’s IRQ pin. V
TST
ranges from 7 V to 9 V, depending on operating V
DD
level. The V
TST
level
enables the mode selection logic and internal operating conditions for the
monitor mode.
COM/PTA0 Since all M68HC908 MCUs do not have a dedicated asynchronous serial
communications interface (SCI), a software-based serial protocol is coded into
each M68HC08 Family’s monitor ROM. This serial interface is designed to
communicate with a host computer’s RS232 serial port at 9600 baud or other
standard PC serial baud rate. The MCU’s serial input and output are
time-shared on a single I/O port pin, usually port A bit 0 (PTA0), to keep
pin-count to a minimum. (See data sheet for specific pin.) A later section will
cover the physical interface to connect this bidirectional pin to a PC.
Mode Select Signals
(MOD1, MOD0, DIV4,
SSEL)
Along with the high voltage on the IRQ
pin, up to four port pins are used to
configure the monitor mode operating state. Two pins, sometimes referred to
as MOD0 and MOD1, are always used as mode select pins. Two more pins are
reserved for bus clock divider selection and an alternate security byte entry
enable. These four pins only need to be at their valid logic levels at the rising
edge of the reset pin for monitor mode entry. They revert to general-purpose
I/O pins as soon as the mode is selected so that maximum I/O functionality is
available in monitor mode.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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