Technical information

AN2317/D
10 Low-Cost Programming and Debugging Options for M68HC08 MCUs
Simpler Monitor Mode
Circuit
A simpler implementation of the monitor mode circuit of Figure 4 is shown in
Figure 5. The two 74HC125 buffers are replaced by a resistor and diode. When
PTA0 is outputting a 1, the input at the MAX232 pin 10 is held high. When PTA0
is outputting a 0, the input at pin 10 is driven low. The RS232 level at pin 8 is
idling low which drives pin 9 to a logic one. This high level is blocked by the
diode so there is no bus conflict. As an input, PTA0 idles high whenever pin 9
is high. When the MAX232 pin 9 goes low, the diode provides the path to pull
the PTA0 input low.
Figure 5. Simpler Monitor Mode Circuit
10 k
10 k
10 k
10 k
RST
IRQ
PTA0
OSC1
16
15
2
6
V
DD
C5
MAX232
V+
V–
V
DD
C4
10 k
0.1 µF
V
DDAD
9.8304 MHz
C1+
C1–
5
4
C2
C2+
C2–
+
3
1
C1
+
+
+
C3
V
DD
8
7
DB9
2
3
5
10
9
+
MC68HC908
N.C.
OSC2
1 k
9.1 V
V
TST
V
DDA
V
DD
V
SS
V
SSA
V
SSAD
V
DD
DIV4
MOD0
MOD1
SSEL
1N4148
1 k
V
CC
GND
10 k
V
DD
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc
.
..