User`s manual

Engineering Bulletin
EB183 — Rev. 1.0
4 MOTOROLA
FLASH EEPROM
Control Register
The FEECTL register (located at $00F7) controls the actual
programming and erasing of the FLASH EEPROM. In this register, five
bits are used to control the FLASH. All bits are 0 upon reset.
FEESWAI
FEESWAI (bit 4) controls the behavior of the FLASH EEPROM clock
while in wait mode.
SVFP
SVFP (bit 3), the V
FP
status bit, is set when V
FP
is at or above normal
programming voltage levels; clear otherwise (read only)
ERAS
ERAS (bit 2), when set, configures the array for erasure.
LAT
LAT (bit 1), when set, enables the programming latches.
ENPE
ENPE (bit 0), when set, applies the programming/erase voltage to the
array.
Address: $00F7
Bit 7 654321Bit 0
Read:
0 0 0 FEESWAI SVFP ERAS LAT ENPE
Write:
Reset:
00000000
Figure 4. FLASH EEPROM Control Register (FEECTL)