Order this document by EB183/D REV. 1.0 Motorola Semiconductor Engineering Bulletin EB183 Erasing and Programming the FLASH EEPROM on the MC68HC912B32 By Matt Ruff M68HC11 and M68HC12 Applications Austin, Texas Introduction This document outlines basic routines to program the FLASH EEPROM through the background debug mode interface (BDM) using a Motorola serial debug interface (SDIL) and the SDBUG12 (version 2.15) software from P & E Microcomputer Systems, Inc.
Engineering Bulletin FLASH EEPROM Control Block The FLASH EEPROM is controlled by a 4-byte register block, which is located at address $00F4 upon reset. Within this block are four singlebyte registers: • Lock control register (FEELCK) • Module configuration register (FEEMCR) • Module test register (FEETST) • Module control register (FEECTL) For more detail on these control registers, refer to Section 7.
Engineering Bulletin FLASH EEPROM Control Block FLASH EEPROM Module Configuration Register The FEEMCR register (located at $00F5) contains only the BOOTP bit (bit 0), which protects the 2-Kbyte boot block (1 Kbyte in early mask sets G86W or G75R) located at $7800–$7FFF or $F800–$FFFF, depending on the mapped location of the FLASH array at power-up. This bit must be cleared, after the FEELCK (LOCK bit) is cleared, in order to write or erase the boot block.
Engineering Bulletin FLASH EEPROM Control Register The FEECTL register (located at $00F7) controls the actual programming and erasing of the FLASH EEPROM. In this register, five bits are used to control the FLASH. All bits are 0 upon reset. Address: $00F7 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 FEESWAI SVFP ERAS LAT ENPE 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 4.
Engineering Bulletin Hardware Configuration Hardware Configuration Setting up the Debugging Hardware Since programming the FLASH EEPROM takes a finite amount of time and is dependent on a reliable programming voltage from an exterior source, it is difficult to tell if the procedure worked immediately. To simplify the debugging of the process, try using a few hardware tricks that are listed in this bulletin.
Engineering Bulletin Software Considerations Using SDBUG12 to manipulate the FLASH EEPROM requires some special considerations. First, a few bugs in some versions of the software can cause some confusion when manipulating the FLASH memory array. The memory display windows sometimes do not refresh properly, especially when manually erasing the array by manipulating the control registers using the mm command.
Engineering Bulletin Erasing the FLASH Array Erasing the FLASH Array This code segment follows the recommended procedure for erasing the FLASH array. Following the code is a flowchart which outlines this same procedure. The general idea is to apply the erase voltage to the FLASH module within the chip (by setting the ENPE bit), set the erase flag, write to any location in the array, then check to make sure the entire array is erased.
Engineering Bulletin STEP2 STEP3 STEP4 STEP5 STEP6 STEP7 MOVB BRCLR LDAB STAB BSET JSR BCLR JSR LDAA CMPA BNE #$06,FEECTL ;Set ERAS and set LAT in FEECTL FEECTL,$08,ERROR ;If Vfp not present, output an error #$FF FEESTART,X ;Write data to a valid Flash address FEECTL,$01 ;Apply erase voltage (Set ENPE) dly_100ms ;Delay time for erase pulse (Tepulse) FEECTL,$01 ;Remove erase voltage (Clear ENPE) dly_10ms ;Delay for high voltage turn off (Tverase) #$01 MARGINF ;Is margin flag set?? NOFLAG ;If not, go bump
Engineering Bulletin Erasing the FLASH Array ;-----------------------------------------------;---Read and Verify Erase subroutine ---;-----------------------------------------------READARRY LDY #$FFFF LDX #FEESTART LOOP CPY 0,X ;Is this word erased? BNE EXITverf ;If not, leave without setting flag CPX #FEEEND ;Are we at the end of the array? BEQ EXITverf INX ;Go to the next address INX BRA LOOP INC ERASED ;Set erased flag EXITverf RTS ;-----------------------------------------------;--------Error Subroutin
Engineering Bulletin START ERASE TURN ON VFP CLEAR MARGIN FLAG CLEAR ERASE PULSE COUNTER (nEP) SET ERAS SET LAT WRITE TO ARRAY SET ENPE DELAY FOR DURATION OF ERASE PULSE (tEPULSE) CLEAR ENPE SET MARGIN FLAG DELAY BEFORE VERIFY (tVERASE) IS MARGIN FLAG SET? NO INCREMENT nEP COUNTER READ ARRAY YES DECREMENT nEP COUNTER ARRAY ERASED? YES NO NO nEP = 0? nEP = 5? YES ARRAY ERASED? NO YES NO YES CLEAR LAT TURN OFF VFP ARRAY ERASED ARRAY FAILED TO ERASE Figure 5.
Engineering Bulletin Programming the FLASH Array Programming the FLASH Array The following code segment follows the recommended procedure for programming the FLASH array. Following the code is a flowchart which outlines this same procedure. The general idea is to apply the programming voltage to the FLASH module within the chip (by setting the ENPE bit), set the programming latches, write the desired byte/word to the location in the array, then check to make sure the location is programmed properly.
Engineering Bulletin START LDS BRCLR LDX #$B00 ;(Turn on your Vfp power supply to board) FEECTL,$08,ERROR ;If Vfp not present, output an error #$0000 LOOP CLR CLR MOVB LDAB STAB BSET JSR BCLR JSR LDAA CMPA BNE Npp MARGINF #$02,FEECTL DATA,X FEESTART,X FEECTL,$01 dly_22us FEECTL,$01 dly_10us #$01 MARGINF NOFLAG ;Clear number of pulses ;Clear margin flag ;Clear ERAS and set LAT in FEECTL YESFLAG DEC LDAA CMPA BNE STEP9 LDAA CMPA BNE STEP10 BCLR INX CMPA BNE BRA Npp #$00 Npp STEP4 FEESTART,X DATA,X ERR
Engineering Bulletin Programming the FLASH Array ;-----------------------------------------------;--------Error Subroutine ------------;-----------------------------------------------ERROR: MOVB #$00,$0000 ;Clear Port A MOVB #$FF,$0002 ;Set DDRA to outputs BLINK MOVB #$01,$0000 ;Turn PA0 on for error output BSR dly_100ms BSR dly_100ms BSR dly_100ms MOVB #$00,$0000 ;Turn PA0 off BSR dly_100ms BSR dly_100ms BSR dly_100ms BRA BLINK ; Repeat ad nauseum....
Engineering Bulletin START PROG TURN ON VFP CLEAR MARGIN FLAG CLEAR PROGRAM PULSE COUNTER (nPP) CLEAR ERAS SET LAT WRITE DATA TO ADDRESS SET ENPE DELAY FOR DURATION OF PROGRAM PULSE (tPPULSE) CLEAR ENPE SET MARGIN FLAG DELAY BEFORE VERIFY (tVPROG) IS MARGIN FLAG SET? NO INCREMENT nPP COUNTER READ LOCATION YES DECREMENT nPP COUNTER DATA CORRECT? YES NO NO nPP = 0? nPP = 50? YES DATA CORRECT? NO YES NO YES CLEAR LAT GET NEXT ADDRESS/DATA NO LOCATION FAILED TO PROGRAM DONE? YES TURN OFF VFP D
Engineering Bulletin Conclusion Conclusion This bulletin gives an overview of the basics of erasing and programming the FLASH array on the MC68HC912B32 microcontroller. Knowing these basics, it is easy to progress to writing a bootloader, designing a field programming unit, or anything else needed to manipulate the FLASH memory. For an example of a serial bootloader for this microcontroller, refer to Serial Bootloader for Reprogramming the MC68HC912B32 FLASH EEPROM (Motorola order number AN1718/D).
N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D Engineering Bulletin Motorola reserves the right to make changes without further notice to any products herein.
