Technical data
MC68HC912B32 MOTOROLA
MC68HC912B32TS/D 9
3 Pinout and Signal Descriptions
3.1 MC68HC912B32 Pin Assignments
The MC68HC912B32 is available in a 80-pin quad flat pack (QFP). Most pins perform two or more func-
tions, as described in the 3.3 Signal Descriptions. Figure 3 shows pin assignments. Shaded pins are
power and ground.
Figure 3 Pin Assignments for MC68HC912B32
MC68HC912B32
80-PIN QFP
HC12 80QFP
PP5
PP4
PW3 / PP3
PW2 / PP2
PW1/ PP1
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PA2 / DATA10 / ADDR10
PA3 / DATA11 / ADDR11
PA4 / DATA12 / ADDR12
PA5 / DATA13 / ADDR13
PA6 / DATA14 / ADDR14
PA7 / DATA15 / ADDR15
PP6
PP7
ADDR0 / DATA0 / PB0
ADDR1 / DATA1 / PB1
ADDR2 / DATA2 / PB2
SMODN / T
AGHI/ BKGD
PAI / IOC7 / PT7
IOC6 / PT6
IOC5 / PT5
IOC4 / PT4
IOC3 / PT3
IOC2 / PT2
IOC1 / PT1
IOC0 / PT0
ADDR9 / DATA9 / PA1
XIRQ
/ PE0
IRQ
/V
PP
/ PE1
R/W
/ PE2
LSTRB
/ TAGLO / PE3
XTAL
EXTAL
RESET
V
DDX
V
SSX
ECLK / PE4
MODA / IPIPE0 / PE5
MODB / IPIPE1 / PE6
DBE
/ PE7
ADDR7 / DATA7 / PB7
ADDR6 / DATA6 / PB6
ADDR5 / DATA5 / PB5
ADDR4 / DATA4 / PB4
ADDR3 / DATA3 / PB3
V
DD
V
SS
PW0/ PP0
V
SSA
V
DDA
PAD7 / AN7
PAD6 / AN6
PAD5 / AN5
PAD4 / AN4
PAD3 / AN3
PAD2 / AN2
PAD1 / AN1
PAD0 / AN0
V
RL
V
RH
V
SS
V
DD
PS0 / RxD
PS1 / TxD
PS2
PS3
PS4 / SDI/MISO
PS5 / SDO/MOSI
PS6 / SCK
PS7 / CS
/SS
V
FP
PDLC6
PDLC5
PDLC4
PDLC3
PDLC2
PDLC1 / DLCTx
PDLC0 / DLCRx
V
SSX
V
DDX
ADDR8 / DATA8 / PA0
PORT AD
PORT A*
PORT B
PORT EPORT E
PORT DLC
PORT S
PORT P
PORT TPORT T
* In narrow mode, high and low data bytes are multiplexed in alternate bus cycles on port A.