Technical data

MOTOROLA MC68HC912B32
84 MC68HC912B32TS/D
Figure 20 Serial Communications Interface Block Diagram
13.2.1 Data Format
The serial data format requires the following conditions:
• An idle-line in the high state before transmission or reception of a message.
• A start bit (logic zero), transmitted or received, that indicates the start of each character.
• Data that is transmitted or received least significant bit (LSB) first.
• A stop bit (logic one), used to indicate the end of a frame. (A frame consists of a start bit, a char-
acter of eight or nine data bits and a stop bit.)
• A BREAK is defined as the transmission or reception of a logic zero for one frame or more.
• This SCI supports hardware parity for transmit and receive.
Rx Baud Rate
Tx Baud Rate
MCLK
DIVIDER
10-11 BIT SHIFT REG
MSB
TxD BUFFER/SC0DRL
TxMTR CONTROL
SC0CR2/SCI CTL 2
SC0CR1/SCI CTL 1
SC0SR1/INT STATUS
DATA RECOVERY
10-11 BIT SHIFT REG
TxD BUFFER/SC0DRL
SC0BD/SELECT
LSB
RxD
TxD
PIN CONTROL / DDRS / PORT S
WAKE-UP LOGICSC0CR1/SCI CTL 1
SC0SR1/INT STATUS
SC0CR2/SCI CTL 2
INT REQUEST LOGIC
MSB LSB
INT REQUEST LOGIC
SCI RECEIVER
SCI TRANSMITTER
DATA BUS
PARITY
DETECT
PARITY
GENERATOR
HC12B32 SCI BLOCK
TO
INTERNAL
LOGIC
BAUD RATE
CLOCK
PS0
PS1