Technical data

MC68HC912B32 MOTOROLA

MC68HC912B32TS/D 83

13 Serial Interface

The serial interface of the MC68HC912B32 consists of two independent serial I/O sub-systems: the se-

rial communication interface (SCI) and the serial peripheral interface (SPI). Each serial pin shares func-

tion with the general-purpose port pins of port S. The SCI is an NRZ type system that is compatible with

standard RS-232 systems. The SCI system has a single wire operation mode which allows the unused

pin to be available as general-purpose I/O. The SPI subsystem, which is compatible with the M68HC11

SPI, includes new features such as SS output and bidirectional mode.

13.1 Block Diagram

Figure 19 Serial Interface Block Diagram

13.2 Serial Communication Interface (SCI)

The serial communication interface on the MC68HC912B32 is an NRZ format (one start, eight or nine

data, and one stop bit) asynchronous communication system with independent internal baud rate gen-

eration circuitry and an SCI transmitter and receiver. It can be configured for eight or nine data bits (one

of which may be designated as a parity bit, odd or even). If enabled, parity is generated in hardware for

transmitted and received data. Receiver parity errors are flagged in hardware. The baud rate generator

is based on a modulus counter, allowing flexibility in choosing baud rates. There is a receiver wake-up

feature, an idle line detect feature, a loop-back mode, and various error detection features. Two port

pins provide the external interface for the transmitted data (TXD) and the received data (RXD).

SCI

I/O

SPI

DDRS/IOCTLR

PORT S I/O DRIVERS

SERIAL

HC12B32 SI BLOCK

INTERFACE

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

RxD

TxD

MISO/SISO

MOSI/MOMI

SCK

CS/SS

I/O