Technical data

MC68HC912B32 MOTOROLA
MC68HC912B32TS/D 81
Full count register access should take place in one clock cycle. A separate read/write for high byte and
low byte will give a different result than accessing them as a word.
Read or write anytime.
Read anytime. Write only in special mode (SMODN = 0)
TCBYP — Timer Divider Chain Bypass
0 = Normal operation
1 = The 16-bit free-running timer counter is divided into two 8-bit halves and the prescaler is by-
passed. The clock drives both halves directly.
PCBYP — Pulse Accumulator Divider Chain Bypass
0 = Normal operation
1 = The 16-bit pulse accumulator counter is divided into two 8-bit halves and the prescaler is by-
passed. The clock drives both halves directly.
PORTT can be read anytime. When configured as an input, a read will return the pin level. When con-
figured as output, a read will return the latched output data.
NOTE
Writes do not change pin state when the pin is configured for timer output. The min-
imum pulse width for pulse accumulator input should always be greater than two
module clocks due to input synchronizer circuitry. The minimum pulse width for the
input capture should always be greater than the width of two module clocks due to
input synchronizer circuitry.
PACNT — 16-Bit Pulse Accumulator Count Register $00A2–$00A3
Bit 7 6 5 4 3 2 1 Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
RESET: 0 0 0 0 0 0 0 0
TIMTST — Timer Test Register $00AD
Bit 7 6 5 4 3 2 1 Bit 0
0 0 0 0 0 0 TCBYP PCBYP
RESET: 0 0 0 0 0 0 0 0
PORTT — Timer Port Data Register $00AE
Bit 7 6 5 4 3 2 1 Bit 0
PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0
TIMER I/OC7 I/OC6 I/OC5 I/OC4 I/OC3 I/OC2 I/OC1 I/OC0
PA PAI