Technical data

MOTOROLA MC68HC912B32
8 MC68HC912B32TS/D
2.4 Indexed Addressing Modes
The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y
index register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after
the instruction opcode. The postbyte and extensions do the following tasks:
• Specify which index register is used
• Determine whether a value in an accumulator is used as an offset
• Enable automatic pre- or post-increment or decrement
• Specify use of 5-bit, 9-bit, or 16-bit signed offsets
2.5 Opcodes and Operands
The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated address-
ing mode to the CPU. Several opcodes are required to provide each instruction with a range of address-
ing capabilities.
Only 256 opcodes would be available if the range of values were restricted to the number that can be
represented by 8-bit binary numbers. To expand the number of opcodes, a second page is added to the
opcode map. Opcodes on the second page are preceded by an additional byte with the value $18.
To provide additional addressing flexibility, opcodes can also be followed by a postbyte or extension
bytes. Postbytes implement certain forms of indexed addressing, transfers, exchanges, and loop prim-
itives. Extension bytes contain additional program information such as addresses, offsets, and immedi-
ate data.
Table 3 Summary of Indexed Operations
Postbyte
Code (xb)
Source Code
Syntax
Comments
rr; 00 = X, 01 = Y, 10 = SP, 11 = PC
rr0nnnnn ,r
n,r
−n,r
5-bit constant offset n = –16 to +15
r can specify X, Y, SP, or PC
111rr0zs n,r
−n,r
Constant offset (9- or 16-bit signed)
z- 0 = 9-bit with sign in LSB of postbyte(s) -256 < n < 255
1 = 16-bit 0 < n < 65,535
if z = s = 1, 16-bit offset indexed-indirect (see below)
r can specify X, Y, SP, or PC
111rr011 [n,r]
16-bit offset indexed-indirect
rr can specify X, Y, SP, or PC 0 < n < 65,535
rr1pnnnn n,−r
n,+r
n,r−
n,r+
Auto pre-decrement/increment or Auto post-decrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
r can specify X, Y, or SP (PC not a valid choice)
+8 = 0111
…
+1 = 0000
-1 = 1111
…
-8 = 1000
111rr1aa A,r
B,r
D,r
Accumulator offset (unsigned 8-bit or 16-bit)
aa- 00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
r can specify X, Y, SP, or PC
111rr111 [D,r]
Accumulator D offset indexed-indirect
r can specify X, Y, SP, or PC