Technical data

MOTOROLA MC68HC912B32
78 MC68HC912B32TS/D
The newly selected prescale factor will not take effect until the next synchronized edge where all pres-
cale counter stages equal zero.
TFLG1 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write a one
to the bit.
Read anytime. Write used in the clearing mechanism (set bits cause corresponding bits to be cleared).
Writing a zero will not affect current status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel ($90–$9F) will cause the corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel “n” Flag.
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, set the bit
to one.
Read anytime. Write used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000. This bit is cleared automatically by
a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.)
TFLG1 — Timer Interrupt Flag 1 $008E
Bit 7 6 5 4 3 2 1 Bit 0
C7F C6F C5F C4F C3F C2F C1F C0F
RESET: 0 0 0 0 0 0 0 0
TFLG2 — Timer Interrupt Flag 2 $008F
Bit 7 6 5 4 3 2 1 Bit 0
TOF 0 0 0 0 0 0 0
RESET: 0 0 0 0 0 0 0 0
TC0 — Timer Input Capture/Output Compare Register 0 $0090–$0091
Bit 7 6 5 4 3 2 1 Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
TC1 — Timer Input Capture/Output Compare Register 1 $0092–$0093
Bit 7 6 5 4 3 2 1 Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
TC2 — Timer Input Capture/Output Compare Register 2 $0094–$0095
Bit 7 6 5 4 3 2 1 Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0