Technical data

MOTOROLA MC68HC912B32
76 MC68HC912B32TS/D
Read or write anytime.
OMn — Output Mode
OLn — Output Level
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a
successful OCn compare. When either OMn or OLn is one, the pin associated with OCn becomes an
output tied to OCn regardless of the state of the associated DDRT bit.
Read or write anytime.
EDGnB, EDGnA — Input Capture Edge Control
These eight pairs of control bits configure the input capture edge detector circuits.
TCTL1 — Timer Control Register 1 $0088
Bit 7 6 5 4 3 2 1 Bit 0
OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4
RESET: 0 0 0 0 0 0 0 0
TCTL2 — Timer Control Register 2 $0089
Bit 7 6 5 4 3 2 1 Bit 0
OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0
RESET: 0 0 0 0 0 0 0 0
Table 24 Compare Result Output Action
OMn OLn Action
0 0 Timer disconnected from output pin logic
0 1 Toggle OCn output line
1 0 Clear OCn output line to zero
1 1 Set OCn output line to one
TCTL3 — Timer Control Register 3 $008A
Bit 7 6 5 4 3 2 1 Bit 0
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
RESET: 0 0 0 0 0 0 0 0
TCTL4 — Timer Control Register 4 $008B
Bit 7 6 5 4 3 2 1 Bit 0
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
RESET: 0 0 0 0 0 0 0 0
Table 25 Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)