Technical data

MC68HC912B32 MOTOROLA
MC68HC912B32TS/D 71
PSBCK — PWM Stops while in Background Mode
0 = Allows PWM to continue while in background mode.
1 = Disable PWM input clock when the part is in background mode.
Read anytime but write only in special mode (SMODN = 0). These bits are available only in special
mode and are reset in normal mode.
DISCR — Disable Reset of Channel Counter on Write to Channel Counter
0 = Normal operation. Write to PWM channel counter will reset channel counter.
1 = Write to PWM channel counter does not reset channel counter.
DISCP — Disable Compare Count Period
0 = Normal operation
1 = In left-aligned output mode, match of period does not reset the associated PWM counter regis-
ter.
In center-aligned output mode, match of period does not change the associated PWM counter
direction.
DISCAL — Disable Load of Scale-Counters on Write to the Associated Scale-Registers
0 = Normal operation
1 = Write to PWSCAL0 and PWSCAL1 does not load scale counters
PWM functions share port P pins 3 to 0 and take precedence over the general-purpose port when en-
abled. PORTP can be read anytime. When configured as input, a read will return the pin level. When
configured as output, a read will return the latched output data.
A write will drive associated pins only if configured for output and the corresponding PWM channel is
not enabled.
After reset, all pins are general-purpose, high-impedance inputs.
DDRP determines pin direction of port P when used for general-purpose I/O. When cleared, I/O pin is
configured for input. When set, I/O pin is configured for output. Read and write anytime.
PWTST — PWM Special Mode Register (“Test”) $0055
Bit 7 6 5 4 3 2 1 Bit 0
DISCR DISCP DISCAL 0 0 0 0 0
RESET: 0 0 0 0 0 0 0 0
PORTP — Port P Data Register $0056
Bit 7 6 5 4 3 2 1 Bit 0
PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0
PWM – – – – PWM3 PWM2 PWM1 PWM0
RESET: – – – – – – – –
DDRP — Port P Data Direction Register $0057
Bit 7 6 5 4 3 2 1 Bit 0
DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDP0
RESET: 0 0 0 0 0 0 0 0