Technical data

MC68HC912B32 MOTOROLA
MC68HC912B32TS/D 65
Figure 17 PWM Clock Sources
11.1 PWM Register Description
Read and write anytime.
CON23 — Concatenate PWM Channels 2 and 3
When concatenated, channel 2 becomes the high-order byte and channel 3 becomes the low-order
byte. Channel 2 output pin is used as the output for this 16-bit PWM (bit 2 of port P). Channel 3 clock-
select control bits determines the clock source.
0 = Channels 2 and 3 are separate 8-bit PWMs.
1 = Channels 2 and 3 are concatenated to create one 16-bit PWM channel.
PWCLK — PWM Clocks and Concatenate $0040
Bit 7 6 5 4 3 2 1 Bit 0
CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2 PCKB1 PCKB0
RESET: 0 0 0 0 0 0 0 0
8-BIT DOWN COUNTER
PCLK2
MUX
PCLK3
MUX
CLOCK TO PWM
CHANNEL 2
CLOCK TO PWM
CHANNEL 3
÷ 2
PWSCNT1
8-BIT SCALE REGISTER
PWSCAL1
CLOCK B
CLOCK S1**
**CLOCK S1 = (CLOCK B)/2, (CLOCK B)/4, (CLOCK B)/6,... (CLOCK B)/512
÷ 2
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
8-BIT DOWN COUNTER
PCLK0
MUX
PCLK1
MUX
CLOCK TO PWM
CHANNEL 0
CLOCK TO PWM
CHANNEL 1
÷ 2
PWSCNT0
8-BIT SCALE REGISTER
PWSCAL0
CLOCK A
CLOCK S0*
*CLOCK S0 = (CLOCK A)/2, (CLOCK A)/4, (CLOCK A)/6,... (CLOCK A)/512
REGISTER: BITS:
PCKB2,
PCKB0
PCKB1,
= 0
= 0
BITS:
PCKA2,
PCKA0
PCKA1,
PWPRES
PSBCK
LIMBDM
PCLK
PSBCK IS BIT 0 OF PWCTL REGISTER.
INTERNAL SIGNAL LIMBDM IS ONE IF THE MCU IS IN BACKGROUND DEBUG MODE.