Technical data

MOTOROLA MC68HC912B32
64 MC68HC912B32TS/D
Figure 16 Block Diagram of PWM Center-Aligned Output Channel
GATE
PWCNTx
8-BIT COMPARE =
PWDTYx
8-BIT COMPARE =
PWPERx
RESET
FROM PORT P
DATA REGISTER
TO PIN
DRIVER
PPOLx
CLOCK SOURCE
(PCLK)
(CLOCK EDGE SYNC)
UP/DOWN
CENTR = 1
MUX
MUX
T
Q
Q
PWDTY
PWENx
PPOL = 0
PPOL = 1
(DUTY CYCLE)
(PERIOD)
PWPER
× 2
(PWPER − PWDTY) × 2
PWDTY