Technical data

MOTOROLA MC68HC912B32
62 MC68HC912B32TS/D
Figure 13 Clock Chain for TIM
Figure 14 Clock Chain for SPI, ATD and BDM
BITS: PR2, PR1, PR0
PCLK
1:0:0
1:0:1
1:1:0
1:1:1
TO TIM
COUNTER
PORT T7
PAMOD
PACLK
PULSE ACC
LOW BYTE
PACLK/256
PULSE ACC
HIGH BYTE
PACLK/65536
(PAOV)
GATE
LOGIC
BITS: PAEN, CLK1, CLK0
0:x:x
TEN
PAEN
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
REGISTER: PACTL
REGISTER: TMSK2
HC12 CLOCK CHAIN TIM
PCLK
BITS: SPR2, SPR1, SPR0
SPI
BIT RATE
5-BIT MODULUS
COUNTER (PR0-PR4)
TO ATD
ECLK
BKGD
BDM BIT CLOCK:
Receive: Detect falling edge,
count 12 E clocks, Sample input
Transmit 1: Detect falling edge,
count 6 E clocks while output is
high impedance, drive out 1 E
cycle pulse high, high imped-
ance output again
Transmit 0: Detect falling edge,
drive out low, count 9 E clocks,
drive out 1 E cycle pulse high,
high impedance output
PIN
SYNCHRONIZER
LOGIC
BKGD IN
BKGD OUT
BKGD DIRECTION
÷ 2
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
REGISTER: SP0BR
HC12 CLOCK CHAIN SPI ATD BDM