Technical data

MOTOROLA MC68HC912B32
60 MC68HC912B32TS/D
Always reads $00.
Writing $55 to this address is the first step of the COP watchdog sequence.
Writing $AA to this address is the second step of the COP watchdog sequence. Other instructions may
be executed between these writes but both must be completed in the correct order prior to time-out to
avoid a watchdog reset. Writing anything other than $55 or $AA causes a COP reset to occur.
10.6 Clock Divider Chains
Figure 11, Figure 12, Figure 13, and Figure 14 summarize the clock divider chains for the various pe-
ripherals on the MC68HC912B32.
Figure 11 Clock Divider Chain
Table 21 COP Watchdog Rates (RTBYP = 0)
CR2 CR1 CR0 Divide E By:
At E = 4.0 MHz
Time-Out
–0 to +2.048 ms
At E = 8.0 MHz
Time-Out
–0 to +1.024 ms
0 0 0 OFF OFF OFF
001
2
13
2.048 ms 1.024 ms
010
2
15
8.1920 ms 4.096 ms
011
2
17
32.768 ms 16.384 ms
100
2
19
131.072 ms 65.536 ms
101
2
21
524.288 ms 262.144 ms
110
2
22
1.048 s 524.288 ms
111
2
23
2.097 s 1.048576 s
COPRST — Arm/Reset COP Timer Register $0017
Bit 7 6 5 4 3 2 1 Bit 0
Bit 7 6 5 4 3 2 1 Bit 0
RESET: 0 0 0 0 0 0 0 0
OSCILLATOR
AND
CLOCK
GENERATOR
EXTAL
XTAL
SYSCLK
T CLOCK
GENERATOR
TO CPU
E AND P CLOCK
GENERATOR
ECLK
PCLK
TO BDM,
BUSES, SPI,
ATD, SCI, TIM,
PULSE ACC,
RTI, COP,
PWM, BDLC
TCLKs
HC912B32 CLOCK DIV CHAIN
÷ 2