Technical data

MC68HC912B32 MOTOROLA
MC68HC912B32TS/D 53
9.3 Interrupt Control and Priority Registers
IRQE — IRQ Select Edge Sensitive Only
0 = IRQ configured for low-level recognition.
1 = IRQ configured to respond only to falling edges (on pin PE1/IRQ).
IRQE can be read anytime and written once in normal modes. In special modes, IRQE can be read any-
time and written anytime, except the first write is ignored.
IRQEN — External IRQ Enable
The IRQ pin has an internal pull-up.
0 = External IRQ pin disconnected from interrupt logic
1 = External IRQ
pin connected to interrupt logic
IRQEN can be read and written anytime in all modes.
DLY — Enable Oscillator Start-Up Delay on Exit from STOP
The delay time of about 4096 cycles is based on the E clock rate.
0 = No stabilization delay imposed on exit from STOP mode. A stable external oscillator must be
supplied.
1 = Stabilization delay is imposed before processing resumes after STOP.
DLY can be read anytime and written once in normal modes. In special modes, DLY can be read and
written anytime.
$FFE8, $FFE9 Timer channel 3 I bit TMSK1 (C3I) $E8
$FFE6, $FFE7 Timer channel 4 I bit TMSK1 (C4I) $E6
$FFE4, $FFE5 Timer channel 5 I bit TMSK1 (C5I) $E4
$FFE2, $FFE3 Timer channel 6 I bit TMSK1 (C6I) $E2
$FFE0, $FFE1 Timer channel 7 I bit TMSK1 (C7I) $E0
$FFDE, $FFDF Timer overflow I bit TMSK2 (TOI) $DE
$FFDC, $FFDD Pulse accumulator overflow I bit PACTL (PAOVI) $DC
$FFDA, $FFDB Pulse accumulator input edge I bit PACTL (PAI) $DA
$FFD8, $FFD9 SPI serial transfer complete I bit SP0CR1 (SPIE) $D8
$FFD6, $FFD7 SCI 0 I bit
SC0CR2
(TIE, TCIE, RIE, ILIE)
$D6
$FFD4, $FFD5 Reserved I bit – $D4
$FFD2, $FFD3 ATD I bit ATDCTL2 (ASCIE) $D2
$FFD0, $FFD1 BDLC I bit BCR1 (IE) $D0
$FF80–$FFCF Reserved I bit – $80–$CE
INTCR — Interrupt Control Register $001E
Bit 7 6 5 4 3 2 1 Bit 0
IRQE IRQEN DLY 0 0 0 0 0
RESET: 0 1 1 0 0 0 0 0
Table 17 Interrupt Vector Map
Vector Address Interrupt Source
CCR
Mask
Local Enable
Register (Bit)
HPRIO Value to
Elevate