Technical data

Section Page
MC68HC912B32 MOTOROLA
MC68HC912B32TS/D 3
1 Introduction
1
1.1 Features ......................................................................................................................................1
1.2 Ordering Information ...................................................................................................................2
1.3 MC68HC912B32 Block Diagram .................................................................................................5
2 Central Processing Unit
6
2.1 Programming Model ....................................................................................................................6
2.2 Data Types ..................................................................................................................................7
2.3 Addressing Modes .......................................................................................................................7
2.4 Indexed Addressing Modes .........................................................................................................8
2.5 Opcodes and Operands ..............................................................................................................8
3 Pinout and Signal Descriptions
9
3.1 MC68HC912B32 Pin Assignments .............................................................................................9
3.2 Power Supply Pins ....................................................................................................................10
3.3 Signal Descriptions ....................................................................................................................11
3.4 Port Signals ...............................................................................................................................15
3.5 Port Pull-Up, Pull-Down and Reduced Drive .............................................................................19
4 Register Block
20
5 Operating Modes and Resource Mapping
25
5.1 Operating Modes .......................................................................................................................25
5.2 Background Debug Mode ..........................................................................................................26
5.3 Internal Resource Mapping .......................................................................................................28
5.4 Memory Maps ............................................................................................................................31
6 Bus Control and Input/Output
32
6.1 Detecting Access Type from External Signals ..........................................................................32
6.2 Registers ...................................................................................................................................32
7 Flash EEPROM
37
7.1 Overview ...................................................................................................................................37
7.2 Flash EEPROM Control Block ...................................................................................................37
7.3 Flash EEPROM Array ...............................................................................................................37
7.4 Flash EEPROM Registers .........................................................................................................37
7.5 Operation ...................................................................................................................................40
7.6 Programming the Flash EEPROM ............................................................................................42
7.7 Erasing the Flash EEPROM ......................................................................................................44
7.8 Program/Erase Protection Interlocks .........................................................................................46
7.9 Stop or Wait Mode .....................................................................................................................46
7.10 Test Mode .................................................................................................................................46
8 EEPROM
47
8.1 EEPROM Programmer’s Model ................................................................................................47
8.2 EEPROM Control Registers ......................................................................................................48
9 Resets and Interrupts
52
9.1 Exception Priority ......................................................................................................................52
9.2 Maskable Interrupts ...................................................................................................................52
9.3 Interrupt Control and Priority Registers .....................................................................................53
9.4 Resets .......................................................................................................................................54
9.5 Effects of Reset .........................................................................................................................54
9.6 Register Stacking ......................................................................................................................55
10 Clock Functions
57
10.1 Clock Sources ...........................................................................................................................57
10.2 Computer Operating Properly (COP) ........................................................................................57
10.3 Real-Time Interrupt ...................................................................................................................57
10.4 Clock Monitor ............................................................................................................................57
10.5 Clock Function Registers ..........................................................................................................58
10.6 Clock Divider Chains .................................................................................................................60
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