Technical data

MOTOROLA MC68HC912B32
14 MC68HC912B32TS/D
Table 5 MC68HC912B32 Signal Description Summary
Pin Name Pin Number Description
PW[3:0] 3–6 Pulse Width Modulator channel outputs.
ADDR[7:0]
DATA[7:0]
25–18
External bus pins share function with general-purpose I/O ports A and B. In sin-
gle chip modes, the pins can be used for I/O. In expanded modes, the pins are
used for the external buses.
ADDR[15:8]
DATA[15:8]
46–39
IOC[7:0] 16–12, 9–7
Pins used for input capture and output compare in the timer and pulse accumu-
lator subsystem.
PAI 16 Pulse accumulator input
AN[7:0] 58–51 Analog inputs for the analog-to-digital conversion module
DBE
26
Data bus control and, in expanded mode, enables the drive control of external
buses during external reads.
MODB, MODA 27, 28 State of mode select pins during reset determine the initial operating mode of the
MCU. After reset, MODB and MODA can be configured as instruction queue
tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins.
IPIPE1, IPIPE0 27, 28
ECLK 29
E-clock is the output connection for the external bus clock. ECLK is used as a
timing reference and for address demultiplexing.
RESET 32
An active low bidirectional control signal, RESET
acts as an input to initialize the
MCU to a known start-up state, and an output when COP or clock monitor causes
a reset.
EXTAL 33
Crystal driver and external clock input pins. On reset all the device clocks are de-
rived from the EXTAL input frequency. XTAL is the crystal output.
XTAL 34
LSTRB
35
Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O. The
low strobe function is the exclusive-NOR of A0 and the internal SZ8 signal. (The
SZ8
internal signal indicates the size 16/8 access.)
T
AGLO 35 Pin used in instruction tagging. See 16 Development Support.
R/W
36
Indicates direction of data on expansion bus. Shares function with general-pur-
pose I/O. Read/write in expanded modes.
IRQ 37
Maskable interrupt request input provides a means of applying asynchronous in-
terrupt requests to the MCU. Either falling edge-sensitive triggering or level-sen-
sitive triggering is program selectable (INTCR register).
XIRQ 38
Provides a means of requesting asynchronous non-maskable interrupt requests
after reset initialization.
BKGD 17
Single-wire background interface pin is dedicated to the background debug func-
tion. During reset, this pin determines special or normal operating mode.
T
AGHI 17 Pin used in instruction tagging. See 16 Development Support.
DLCRx 76 BDLC receive pin
DLCTx 75 BDLC transmit pin
CS
/SS 68 Slave select output for SPI master mode, input for slave mode or master mode.
SCK 67 Serial clock for SPI system.
SDO/MOSI 66 Master out/slave in pin for serial peripheral interface
SDI/MISO 65 Master in/slave out pin for serial peripheral interface
TxD0 62 SCI transmit pin
RxD0 61 SCI receive pin