Technical data

MOTOROLA MC68HC912B32
120 MC68HC912B32TS/D
16.2.4 BDM Registers
Seven BDM registers are mapped into the standard 64-Kbyte address space when BDM is active. The
registers can be accessed with the hardware READ_BD and WRITE_BD commands, but must not be
written during BDM operation. Most users will only be interested in the STATUS register at $FF01; other
registers are only for use by BDM firmware and logic.
The instruction register is discussed for two conditions: when a hardware command is executed and
when a firmware command is executed.
The bits in the BDM instruction register have the following meanings when a hardware command is
executed.
H/F — Hardware/Firmware Flag
0 = Firmware instruction
1 = Hardware instruction
DATA — Data Flag
0 = No data
1 = Data included in command
R/W — Read/Write Flag
0 = Write
1 = Read
BKGND — Hardware request to enter active background mode
0 = Not a hardware background command
1 = Hardware background command (INSTRUCTION = $90)
Table 44 BDM Firmware Commands
Command Opcode (Hex) Data Description
READ_NEXT 62 16-bit data out X = X + 2; Read next word pointed-to by X
READ_PC 63 16-bit data out Read program counter
READ_D 64 16-bit data out Read D accumulator
READ_X 65 16-bit data out Read X index register
READ_Y 66 16-bit data out Read Y index register
READ_SP 67 16-bit data out Read stack pointer
WRITE_NEXT 42 16-bit data in X = X + 2; Write next word pointed-to by X
WRITE_PC 43 16-bit data in Write program counter
WRITE_D 44 16-bit data in Write D accumulator
WRITE_X 45 16-bit data in Write X index register
WRITE_Y 46 16-bit data in Write Y index register
WRITE_SP 47 16-bit data in Write stack pointer
GO 08 None Go to user program
TRACE1 10 None Execute one user instruction then return to BDM
TAGGO 18 None Enable tagging and go to user program
INSTRUCTION — BDM Instruction Register (hardware command bit explanation) (BDM) $FF00
Bit 7 6 5 4 3 2 1 Bit 0
H/F DATA R/W BKGND W/B BD/U 0 0