Technical data

MC68HC912B32 MOTOROLA
MC68HC912B32TS/D 117
Figure 27 BDM Host to Target Serial Bit Timing
Figure 28 BDM Target to Host Serial Bit Timing (Logic 1)
Figure 28 shows the host receiving a logic one from the target MC68HC912B32 MCU. Since the host
is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target E cycles). The host must release the low drive
before the target MCU drives a brief active-high speed-up pulse seven cycles after the perceived start
of the bit time. The host should sample the bit level about ten cycles after it started the bit time.
9 CYCLES
E CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
TARGET SENSES BIT
EARLIEST
START OF
NEXT BIT
SYNCHRONIZATION
UNCERTAINTY
PERCEIVED
START
OF BIT TIME
HOST
TRANSMIT 0
HC12A4 BDM HOST TO TARGET TIM
10 CYCLES
E CLOCK
(TARGET
MCU)
EARLIEST
START OF
NEXT BIT
BKGD PIN
PERCEIVED
START OF BIT
TIME
10 CYCLES
HOST SAMPLES
BKGD PIN
HOST
DRIVE TO
BKGD PIN
TARGET MCU
SPEEDUP PULSE
R-C RISE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HC12A4 BDM TARGET TO HOST TIM 1