Technical data

MC68HC912B32 MOTOROLA
MC68HC912B32TS/D 113
The ATD status registers contain the flags indicating the completion of ATD conversions.
Normally, it is read-only. In special mode, the SCF bit and the CCF bits may also be written.
SCF — Sequence Complete Flag
This bit is set at the end of the conversion sequence when in the single conversion sequence mode
(SCAN = 0 in ATDCTL5) and is set at the end of the first conversion sequence when in the continuous
conversion mode (SCAN = 1 in ATDCTL5). When AFFC = 0, SCF is cleared when a write is performed
to ATDCTL5 to initiate a new conversion sequence. When AFFC = 1, SCF is cleared after the first result
register is read.
CC[2:0] — Conversion Counter for Current Sequence of Four or Eight Conversions
This 3-bit value reflects the contents of the conversion counter pointer in a four or eight count sequence.
This value also reflects which result register will be written next, indicating which channel is currently
being converted.
CCF[7:0] — Conversion Complete Flags
Each of these bits are associated with an individual ATD result register. For each register, this bit is set
at the end of conversion for the associated ATD channel and remains set until that ATD result register
is read. It is cleared at that time if AFFC bit is set, regardless of whether a status register read has been
performed (i.e., a status register read is not a pre-qualifier for the clearing mechanism when AFFC = 1).
Otherwise the status register must be read to clear the flag.
The test registers control various special modes which are used during manufacturing. The test register
can be read or written only in the special modes. In the normal modes, reads of the test register return
zero and writes have no effect.
SAR[9:0] — SAR Data
Reads of this byte return the current value in the SAR. Writes to this byte change the SAR to the value
written. Bits SAR[9:2] reflect the eight SAR bits used during the resolution process for an 8-bit result.
SAR1 and SAR0 are reserved to allow future derivatives to increase ATD resolution to ten bits.
ATDSTAT — ATD Status Register $0066
Bit 7 6 5 4 3 2 1 Bit 0
SCF 0 0 0 0 CC2 CC1 CC0
RESET: 0 0 0 0 0 0 0 0
ATDSTAT — ATD Status Register $0067
Bit 7 6 5 4 3 2 1 Bit 0
CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
RESET: 0 0 0 0 0 0 0 0
ATDTSTH — ATD Test Register $0068
Bit 7 6 5 4 3 2 1 Bit 0
SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2
RESET: 0 0 0 0 0 0 0 0
ATDTSTL — ATD Test Register $0069
Bit 7 6 5 4 3 2 1 Bit 0
SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0
RESET: 0 0 0 0 0 0 0 0