Technical data

MC68HC912B32 MOTOROLA
MC68HC912B32TS/D 107
If a BREAK symbol is received while the BDLC is transmitting or receiving, an invalid symbol interrupt
will be generated. Reading the BSVR register will clear this interrupt condition. The BDLC will wait for
the bus to idle, then wait for SOF.
The BDLC cannot transmit a BREAK symbol. It can only receive a BREAK symbol from the J1850 bus.
Table 37 BDLC J1850 Bus Error Summary
Error Condition BDLC Function
Bus short to V
BATT
The BDLC will not transmit until the bus is idle.
Bus short to ground
Thermal overload will shutdown physical interface.
Fault condition is reflected in BSVR as invalid symbol.
Invalid symbol: BDLC receives
invalid bits (noise)
The BDLC will abort transmission immediately.
Invalid symbol interrupt will be generated.
Framing Error
Invalid symbol interrupt will be generated.
The BDLC will wait for SOF.
CRC Error
CRC error interrupt will be generated.
The BDLC will wait for SOF.
BDLC receives BREAK symbol
The BDLC will wait for the next valid SOF.
Invalid symbol interrupt will be generated.
Invalid Symbol: BDLC sends an
EOD but receives an active symbol
Invalid symbol interrupt will be generated.
The BDLC will wait for SOF.