Technical data

MC68HC912B32 MOTOROLA
MC68HC912B32TS/D 103
Decreases the CPU overhead associated with servicing interrupts while operating a serial communica-
tion protocol. It provides an index offset that is directly related to the BDLC’s current state.
I0, I1, I2, I3 — Interrupt Source
Source of the pending interrupt request. Bits are encoded according to Table 35.
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR register except when the BDLC data register
needs servicing (RDRF, RXIFR, or TDRE conditions). RXIFR and RDRF can only be cleared by a read
of the BSVR register followed by a read of BDR. TDRE can either be cleared by a read of the BSVR
register followed by a write to the BDLC BDR register, or by setting the TEOD bit in BCR2.
Upon receiving a BDLC interrupt, the user may read the value within the BSVR, transferring it to the
CPU’s index register. The value can be used to index a jump table to access a service routine. For ex-
ample:
SERVICE LDX BSVR Fetch State Vector Number
JMP JMPTAB,X Enter service routine,
* (must end in an RTI)
*
JMPTAB JMP SERVE0 Service condition #0
NOP
JMP SERVE1 Service condition #1
NOP
JMP SERVE2 Service condition #2
NOP
.
.
.
JMP SERVE8 Service condition #8
END
NOP instructions are used to align the JMP instructions onto 4-byte boundaries so that the value in the
BSVR may be used intact. Each of the service routines must end with an RTI instruction.
BSVR — BDLC State Vector Register $00F9
Bit 7 6 5 4 3 2 1 Bit 0
0 0 I3 I2 I1 I0 0 0
RESET: 0 0 0 0 0 0 0 0
Table 35 Interrupt Sources
BSVR I3 I2 I1 I0 Interrupt Source Priority
$00 0000 No Interrupts Pending 0 (lowest)
$04 0001 Received EOF 1
$08 0010 Received IFR byte (RXIFR) 2
$0C0011 Rx data register full (RDRF) 3
$10 0100 Tx data register empty (TDRE) 4
$14 0101 Loss of arbitration 5
$18 0110 CRC error 6
$1C0111 Symbol invalid or out of range 7
$20 1000 Wakeup 8 (highest)