User manual
Table Of Contents
- COVER
- TABLE OF CONTENTS
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
- LIST OF FIGURES
- LIST OF TABLES
- Table 2-1. Debugger Address Parameter Format
- Table 2-2. CPU32Bug Exception Vectors
- Table 3-1. Debug Monitor Commands
- Table 4-1. CPU32Bug Assembler Addressing Modes
- Table 5-1. CPU32Bug System Call Routines
- Table 6-1. MCU CPU Diagnostic Tests
- Table 6-2. Memory Diagnostic Tests
- Table B-1. Self-Test Error Messages
- Table C-1. CPU32Bug Customization Area
- Table C-2. MCU SCI Communication Formats
- Table C-3. Rev. A Chip Selection Summary
- Table C-4. Rev. B Chip Selection Summary
- Table C-5. BCC Rev. C Chip Selection Summary
- Table C-6. PFB Rev. C Compatibility
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- 3.1 INTRODUCTION
- 3.2 BLOCK OF MEMORY COMPARE
- 3.3 BLOCK OF MEMORY FILL
- 3.4 BLOCK OF MEMORY MOVE
- 3.5 BREAKPOINT INSERT/DELETE
- 3.6 BLOCK OF MEMORY SEARCH
- 3.7 BLOCK OF MEMORY VERIFY
- 3.8 DATA CONVERSION
- 3.9 DUMP S-RECORDS
- 3.10 GO DIRECT (IGNORE BREAKPOINTS)
- 3.11 GO TO NEXT INSTRUCTION
- 3.12 GO EXECUTE USER PROGRAM
- 3.13 GO TO TEMPORARY BREAKPOINT
- 3.14 HELP
- 3.15 LOAD S-RECORDS FROM HOST
- 3.16 MACRO DEFINE/DISPLAY/DELETE
- 3.17 MACRO EDIT
- 3.18 MACRO EXPANSION LISTING ENABLE/DISABLE
- 3.19 MEMORY DISPLAY
- 3.20 MEMORY MODIFY
- 3.21 MEMORY SET
- 3.22 OFFSET REGISTERS DISPLAY/MODIFY
- 3.23 PRINTER ATTACH/DETACH
- 3.24 PORT FORMAT
- 3.25 REGISTER DISPLAY
- 3.26 COLD/WARM RESET
- 3.27 REGISTER MODIFY
- 3.28 REGISTER SET
- 3.29 SWITCH DIRECTORIES
- 3.30 TRACE
- 3.31 TRACE ON CHANGE OF CONTROL FLOW
- 3.32 TRANSPARENT MODE
- 3.33 TRACE TO TEMPORARY BREAKPOINT
- 3.34 VERIFY S-RECORDS AGAINST MEMORY
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- 5.1 INTRODUCTION
- 5.2 SYSTEM CALL ROUTINES
- 5.2.1 Calculate BCD Equivalent Specified Binary Number
- 5.2.2 Parse Value, Assign to Variable
- 5.2.3 Check for Break
- 5.2.4 Timer Delay Function
- 5.2.5 Unsigned 32 x 32 Bit Divide
- 5.2.6 Erase Line
- 5.2.7 Input Character Routine
- 5.2.8 Input Line Routine
- 5.2.9 Input Serial Port Status
- 5.2.10 Unsigned 32 x 32 Bit Multiply
- 5.2.11 Output Character Routine
- 5.2.12 Output String Using Pointers
- 5.2.13 Print Carriage Return and Line Feed
- 5.2.14 Read Line to Fixed-Length Buffer
- 5.2.15 Read String Into Variable-Length Buffer
- 5.2.16 Return to CPU32Bug
- 5.2.17 Send Break
- 5.2.18 Compare Two Strings
- 5.2.19 Timer Initialization
- 5.2.20 Read Timer
- 5.2.21 Start Timer at T=0
- 5.2.22 Output String with Data
- 5.2.23 Output String Using Character Count
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- 6.1 INTRODUCTION
- 6.2 DIAGNOSTIC MONITOR
- 6.2.1 Monitor Start-Up
- 6.2.2 Command Entry and Directories
- 6.2.3 Help (HE)
- 6.2.4 Self Test (ST)
- 6.2.5 Switch Directories (SD)
- 6.2.6 Loop-On-Error Mode (LE)
- 6.2.7 Stop-On-Error Mode (SE)
- 6.2.8 Loop-Continue Mode (LC)
- 6.2.9 Non-Verbose Mode (NV)
- 6.2.10 Display Error Counters (DE)
- 6.2.11 Clear (Zero) Error Counters (ZE)
- 6.2.12 Display Pass Count (DP)
- 6.2.13 Zero Pass Count (ZP)
- 6.3 UTILITIES
- 6.4 CPU TESTS FOR THE MCU
- 6.5 MEMORY TESTS (MT)
- 6.6 BUS ERROR TEST
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
USER CUSTOMIZATION
M68CPU32BUG REV 1 C-10
Table C-1. CPU32Bug Customization Area (continued)
Offset Default Value Mnemonic Description
Power On Branch Vectors (PWR_XXX)
$90-95 $60FF0000E056 PWR_TBL1 BRA.L to Initialization Table #1 routine. See INITTBL
below.
$96-9B $60FF0000DEE8 PWR_INI BRA.L to MCU (chip selects) initialization routine:
Exit: D7.L = power up status flags (bits 31-8)
Returns to PWR_TTL (no stack usage!).
$9C-A1 $60FF0000E070 PWR_TBL2 BRA.L to Initialization Table #2 routine. See INITTBL
below.
Exit: D7.L = preserved
$A2-A7 $60FF00000004 PWR_TTL BRA.L to title printing routine:
Returns to PWR_TST (no stack usage!).
Exit: D7.L = preserved
$A8-AD $60FF0000D8AA PWR_TST BRA.L to self-test routine:
Exit: D7.B = error code
D7:31-8 = power up status flags
Returns to PWR_GO (no stack usage!).
$AE-B3 $60FF0000D4B4 PWR_GO BRA.L to CPU32Bug start up routine:
Entry: D7.B = 0 for no self-test errors, else it equals
the error code number (see Appendix B).
D7:31-8 = power up status flags
Never returns.
$B4-B9 all $FF’s BRA.L <reserved>
$BA-BF all $FF’s BRA.L <reserved>
$C0-CF all $FF’s <reserved>
USER CUSTOMIZATION
M68CPU32BUG REV 1 C-7
Table C-1. CPU32Bug Customization Area (continued)
Offset Default Value Mnemonic Description
$70 $06 SYPCR_OR Value ORed with contents of SYPCR register at power-
up/reset.
$71 $FF SYPCR_AND Value ANDed with result value after SYPCR_OR and
stored back into SYPCR. This allows user control of the
write-once bits in the SYPCR, i.e., software watchdog,
halt monitor, and bus monitor.
NOTE
Enabling the software watchdog with a short timeout period may cause
CPU32Bug itself to fail when the watchdog is not serviced soon enough. The
failure is constant RESETing before the CPU32Bug> prompt appears, or
RESETing during execution of particular commands.
Disabling the bus monitor timeout period causes CPU32Bug to lock-up on
any unterminated bus cycle, i.e., accessing non-existant memory.
Changing the bus monitor timeout period to too small of a value can cause
problems with slow memory or if the 8-bit bus mode is enabled upon booting.
$72-73 $8000 FCRYSTAL Crystal frequency in Hz (8000 = 32,768). SCI baud
rates are calculated using this value.
$74-77 $FFFFFFFF FEXTAL External clock frequency (in hertz). Only used when
MODCK is held low during RESET to enable the
EXTAL pin. SCI baud rates are calculated using this
value.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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