User manual
Table Of Contents
- COVER
- TABLE OF CONTENTS
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
- LIST OF FIGURES
- LIST OF TABLES
- Table 2-1. Debugger Address Parameter Format
- Table 2-2. CPU32Bug Exception Vectors
- Table 3-1. Debug Monitor Commands
- Table 4-1. CPU32Bug Assembler Addressing Modes
- Table 5-1. CPU32Bug System Call Routines
- Table 6-1. MCU CPU Diagnostic Tests
- Table 6-2. Memory Diagnostic Tests
- Table B-1. Self-Test Error Messages
- Table C-1. CPU32Bug Customization Area
- Table C-2. MCU SCI Communication Formats
- Table C-3. Rev. A Chip Selection Summary
- Table C-4. Rev. B Chip Selection Summary
- Table C-5. BCC Rev. C Chip Selection Summary
- Table C-6. PFB Rev. C Compatibility
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- 3.1 INTRODUCTION
- 3.2 BLOCK OF MEMORY COMPARE
- 3.3 BLOCK OF MEMORY FILL
- 3.4 BLOCK OF MEMORY MOVE
- 3.5 BREAKPOINT INSERT/DELETE
- 3.6 BLOCK OF MEMORY SEARCH
- 3.7 BLOCK OF MEMORY VERIFY
- 3.8 DATA CONVERSION
- 3.9 DUMP S-RECORDS
- 3.10 GO DIRECT (IGNORE BREAKPOINTS)
- 3.11 GO TO NEXT INSTRUCTION
- 3.12 GO EXECUTE USER PROGRAM
- 3.13 GO TO TEMPORARY BREAKPOINT
- 3.14 HELP
- 3.15 LOAD S-RECORDS FROM HOST
- 3.16 MACRO DEFINE/DISPLAY/DELETE
- 3.17 MACRO EDIT
- 3.18 MACRO EXPANSION LISTING ENABLE/DISABLE
- 3.19 MEMORY DISPLAY
- 3.20 MEMORY MODIFY
- 3.21 MEMORY SET
- 3.22 OFFSET REGISTERS DISPLAY/MODIFY
- 3.23 PRINTER ATTACH/DETACH
- 3.24 PORT FORMAT
- 3.25 REGISTER DISPLAY
- 3.26 COLD/WARM RESET
- 3.27 REGISTER MODIFY
- 3.28 REGISTER SET
- 3.29 SWITCH DIRECTORIES
- 3.30 TRACE
- 3.31 TRACE ON CHANGE OF CONTROL FLOW
- 3.32 TRANSPARENT MODE
- 3.33 TRACE TO TEMPORARY BREAKPOINT
- 3.34 VERIFY S-RECORDS AGAINST MEMORY
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- 5.1 INTRODUCTION
- 5.2 SYSTEM CALL ROUTINES
- 5.2.1 Calculate BCD Equivalent Specified Binary Number
- 5.2.2 Parse Value, Assign to Variable
- 5.2.3 Check for Break
- 5.2.4 Timer Delay Function
- 5.2.5 Unsigned 32 x 32 Bit Divide
- 5.2.6 Erase Line
- 5.2.7 Input Character Routine
- 5.2.8 Input Line Routine
- 5.2.9 Input Serial Port Status
- 5.2.10 Unsigned 32 x 32 Bit Multiply
- 5.2.11 Output Character Routine
- 5.2.12 Output String Using Pointers
- 5.2.13 Print Carriage Return and Line Feed
- 5.2.14 Read Line to Fixed-Length Buffer
- 5.2.15 Read String Into Variable-Length Buffer
- 5.2.16 Return to CPU32Bug
- 5.2.17 Send Break
- 5.2.18 Compare Two Strings
- 5.2.19 Timer Initialization
- 5.2.20 Read Timer
- 5.2.21 Start Timer at T=0
- 5.2.22 Output String with Data
- 5.2.23 Output String Using Character Count
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- 6.1 INTRODUCTION
- 6.2 DIAGNOSTIC MONITOR
- 6.2.1 Monitor Start-Up
- 6.2.2 Command Entry and Directories
- 6.2.3 Help (HE)
- 6.2.4 Self Test (ST)
- 6.2.5 Switch Directories (SD)
- 6.2.6 Loop-On-Error Mode (LE)
- 6.2.7 Stop-On-Error Mode (SE)
- 6.2.8 Loop-Continue Mode (LC)
- 6.2.9 Non-Verbose Mode (NV)
- 6.2.10 Display Error Counters (DE)
- 6.2.11 Clear (Zero) Error Counters (ZE)
- 6.2.12 Display Pass Count (DP)
- 6.2.13 Zero Pass Count (ZP)
- 6.3 UTILITIES
- 6.4 CPU TESTS FOR THE MCU
- 6.5 MEMORY TESTS (MT)
- 6.6 BUS ERROR TEST
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION

USER CUSTOMIZATION
M68CPU32BUG REV 1 C-4
9. Power up the newly programmed BCC and note the checksum value indicated.
Repeat steps 1 through 8 above, to set the checksum to this value but with the
changes noted below. The CODESIZE parameter at offset $08 can be altered to make
the checksum valid only over the CPU32Bug half of the EPROM so user code in the
second half can be freely changed. Since a checksum error is simply reported on the
display terminal and code execution continues, it is not mandatory to set the
checksum.
STEP 1: No change.
STEP 2: Change checksum to the value noted on power-up per the command
below where "XXXX" is the value noted.
CPU32Bug>MS 400E XXXX<CR>
STEP 3: Change the filename to C32B1C.MX. To speed up reprogramming, a
temporary file consisting of only the checksum word could be used by
entering DU 400E 400F âTMP.MXâ ,DC000<ALT-F1><CR> after
creating the C32B1C.MX file.
STEP 4: Skip this step.
STEP 5: No change.
STEP 6: Change the filename to C32B1C.MX.
STEP 7: This step is optional.
STEP 8: Only the checksum value needs to be programmed using the indicated
value. Since the checksum was set to the unprogrammed state of the
EPROM ($FFFF), programming can start immediately. DO NOT
ERASE THE BCC EPROM!
10. Power-up the BCC once again. The checksum message should not appear.
11. On the host computer, enter the following commands to update the two CPU32Bug S-
record files so they may be properly archived to a floppy disk for safe keeping:
C>DEL TMP.MX<CR>
C>DEL C32B1.MX<CR>
C>RENAME C32B1C.MX C32B1.MX<CR>
C>COPY C32B*.MX A:<CR>
12. The customization procedure is now complete.
USER CUSTOMIZATION
M68CPU32BUG REV 1 C-5
C.3 CUSTOMIZATION TABLE
Table C-1. CPU32Bug Customization Area
Offset Default Value Mnemonic Description
$00-03 $00002FFC PWR_SSP Power on/reset stack pointer
$04-07 $000E0090 PWR_PC Power on/reset program counter
$08-0B $00020000 CODESIZE Size of CPU32Bug ROM in bytes:
Number of bytes for checksum calculation. Must be
an even number of bytes.
$0C $20 SRECMAX Maximum number of data bytes for S-record created by
DU command
Legal values = 1â255 ($01â$FF).
$0D $FF CHECKALT Checksum alternate:
Change this if CHECKSUM should ever be
calculated as $FFFF.
$0E-0F $3033 CHECKSUM Checksum value:
$FFFF = calculate new checksum value, else
checksum has been set. In either case CPU32Bug
simply reports any error and continues toward the
ready prompt.
Old Chip Select Table (Rev. A BCC + Rev. A PFB)
$10-11
$12-13
$0003
$5830
.CSBAR0
.CSOR0
CS0 base address register value and
. option register value
$14-15
$16-17
$0003
$3830
.CSBAR1
.CSOR1
CS1 base address register value and
. option register value
$18-19
$1A-1B
$0103
$6870
.CSBAR2
.CSOR2
CS2 base address register value and
. option register value
$1C-1D
$1E-1F
$0103
$3030
.CSBAR3
.CSOR3
CS3 base address register value and
. option register value
$20-21
$22-23
$1004
$5870
.CSBAR4
.CSOR4
CS4 base address register value and
. option register value
$24-25
$26-27
$1004
$3870
.CSBAR5
.CSOR5
CS5 base address register value and
. option register value
$28-29
$2A-2B
$FFE8
$783F
.CSBAR6
.CSOR6
CS6 base address register value and
. option register value
$2C-2D
$2E-2F
$0000
$0000
.CSBAR7
.CSOR7
CS7 base address register value and
. option register value
$30-31
$32-33
$FFF8
$680F
.CSBAR8
.CSOR8
CS8 base address register value and
. option register value
$34-35
$36-37
$0000
$0000
.CSBAR9
.CSOR9
CS9 base address register value and
. option register value
$38-39
$3A-3B
$0103
$5030
.CSBAR10
.CSOR10
CS10 base address register value and
. option register value
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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