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USER CUSTOMIZATION

M68CPU32BUG REV 1 C-6

Table C-1. CPU32Bug Customization Area (continued)

Offset Default Value Mnemonic Description

Common Chip Select Table: (Rev. A BCC + Rev. A PFB) &

(Rev. B BCC + Rev. B PFB)

$3C-3D

$3E-3F

$0E04

$68B0

.CSBARBT

.CSORBT

CSBOOT base address register value and

. option register value

New Chip Select Table: (Rev. B BCC + Rev. B PFB)

$40-41

$42-43

$0003

$503E

.CSBAR0

.CSOR0

CS0 base address register value and

. option register value

$44-45

$46-47

$0003

$303E

.CSBAR1

.CSOR1

CS1 base address register value and

. option register value

$48-49

$4A-4B

$0003

$683E

.CSBAR2

.CSOR2

CS2 base address register value and

. option register value

$4C-4D

$4E-4F

$0000

.CSBAR3

.CSOR3

CS3 base address register value and

. option register value

$50-51

$52-53

$FFF8

$680F

.CSBAR4

.CSOR4

CS4 base address register value and

. option register value

$54-55

$56-57

$FFE8

$783F

.CSBAR5

.CSOR5

CS5 base address register value and

. option register value

$58-59

$5A-5B

$1004

$38F0

.CSBAR6

.CSOR6

CS6 base address register value and

. option register value

$5C-5D

$5E-5F

$1004

$58F0

.CSBAR7

.CSOR7

CS7 base address register value and

. option register value

$60-61

$62-63

$0103

$6870

.CSBAR8

.CSOR8

CS8 base address register value and

. option register value

$64-65

$66-67

$0103

$3030

.CSBAR9

.CSOR9

CS9 base address register value and

. option register value

$68-69

$6A-6B

$0103

$5030

.CSBAR10

.CSOR10

CS10 base address register value and

. option register value

$6C-6D $020F MCR_OR Value ORed with contents of MCR register at power-

on/reset.

$6E-6F $DFFF MCR_AND Value ANDed with result value after MCR_OR and

stored back into MCR. If bit 6 (MM bit)of MCR_AND =

0, then module register block is placed at $7FF000.

Otherwise it is placed at $FFF000 (default).

USER CUSTOMIZATION

M68CPU32BUG REV 1 C-3

6. Verify the customized S-record file, C32B1.MX, by entering the command shown

below. The -DC000 offset is required to relocate the verification from the $E0000

base address of the S-records to the RAM change area at $4000.

CPU32Bug>VE -DC000<CR>

Enter the terminal emulator’s escape key to return to the host computer’s operating

system (ALT-F4 for ProComm). Then enter the host command to send the S-record

file to the port where the BCC is connected (type c32b.mx >com1, when the BCC is

connected to the com1 port).

After the file has been sent, restart the terminal emulation program by entering EXIT

on the host computer. Then enter two <CR>’s to signal the CPU32Bug that

verification is complete and the terminal emulator program is ready to receive the

status message.

Verify passes.

CPU32Bug>

7. Verify the main S-record file, C32B23.MX, by entering the command shown below.

No offset is required.

CPU32Bug>VE<CR>

Enter the terminal emulator’s escape key to return to the host computer’s operating

system (ALT-F4 for ProComm). Then enter the host computer command to send the

S-record file to the BCC (type c32b23.mx >com1, when the BCC is connected to the

com1 port).

After the file has been sent, restart the terminal emulation by entering EXIT on the

host computer. Then enter two <CR>’s to signal the CPU32Bug that verification is

complete and the terminal emulator program is ready to receive the status message.

Verify passes.

CPU32Bug>

8. Follow the PROGBCC utility (available on FREEWARE) directions for

reprogramming the BCC EPROM using the two S-record files, C32B1.MX and

C32B23.MX.

eescale S

emiconduct

, I

Freescale Semiconductor, Inc.

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