User manual
Table Of Contents
- COVER
- TABLE OF CONTENTS
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
- LIST OF FIGURES
- LIST OF TABLES
- Table 2-1. Debugger Address Parameter Format
- Table 2-2. CPU32Bug Exception Vectors
- Table 3-1. Debug Monitor Commands
- Table 4-1. CPU32Bug Assembler Addressing Modes
- Table 5-1. CPU32Bug System Call Routines
- Table 6-1. MCU CPU Diagnostic Tests
- Table 6-2. Memory Diagnostic Tests
- Table B-1. Self-Test Error Messages
- Table C-1. CPU32Bug Customization Area
- Table C-2. MCU SCI Communication Formats
- Table C-3. Rev. A Chip Selection Summary
- Table C-4. Rev. B Chip Selection Summary
- Table C-5. BCC Rev. C Chip Selection Summary
- Table C-6. PFB Rev. C Compatibility
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- 3.1 INTRODUCTION
- 3.2 BLOCK OF MEMORY COMPARE
- 3.3 BLOCK OF MEMORY FILL
- 3.4 BLOCK OF MEMORY MOVE
- 3.5 BREAKPOINT INSERT/DELETE
- 3.6 BLOCK OF MEMORY SEARCH
- 3.7 BLOCK OF MEMORY VERIFY
- 3.8 DATA CONVERSION
- 3.9 DUMP S-RECORDS
- 3.10 GO DIRECT (IGNORE BREAKPOINTS)
- 3.11 GO TO NEXT INSTRUCTION
- 3.12 GO EXECUTE USER PROGRAM
- 3.13 GO TO TEMPORARY BREAKPOINT
- 3.14 HELP
- 3.15 LOAD S-RECORDS FROM HOST
- 3.16 MACRO DEFINE/DISPLAY/DELETE
- 3.17 MACRO EDIT
- 3.18 MACRO EXPANSION LISTING ENABLE/DISABLE
- 3.19 MEMORY DISPLAY
- 3.20 MEMORY MODIFY
- 3.21 MEMORY SET
- 3.22 OFFSET REGISTERS DISPLAY/MODIFY
- 3.23 PRINTER ATTACH/DETACH
- 3.24 PORT FORMAT
- 3.25 REGISTER DISPLAY
- 3.26 COLD/WARM RESET
- 3.27 REGISTER MODIFY
- 3.28 REGISTER SET
- 3.29 SWITCH DIRECTORIES
- 3.30 TRACE
- 3.31 TRACE ON CHANGE OF CONTROL FLOW
- 3.32 TRANSPARENT MODE
- 3.33 TRACE TO TEMPORARY BREAKPOINT
- 3.34 VERIFY S-RECORDS AGAINST MEMORY
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- 5.1 INTRODUCTION
- 5.2 SYSTEM CALL ROUTINES
- 5.2.1 Calculate BCD Equivalent Specified Binary Number
- 5.2.2 Parse Value, Assign to Variable
- 5.2.3 Check for Break
- 5.2.4 Timer Delay Function
- 5.2.5 Unsigned 32 x 32 Bit Divide
- 5.2.6 Erase Line
- 5.2.7 Input Character Routine
- 5.2.8 Input Line Routine
- 5.2.9 Input Serial Port Status
- 5.2.10 Unsigned 32 x 32 Bit Multiply
- 5.2.11 Output Character Routine
- 5.2.12 Output String Using Pointers
- 5.2.13 Print Carriage Return and Line Feed
- 5.2.14 Read Line to Fixed-Length Buffer
- 5.2.15 Read String Into Variable-Length Buffer
- 5.2.16 Return to CPU32Bug
- 5.2.17 Send Break
- 5.2.18 Compare Two Strings
- 5.2.19 Timer Initialization
- 5.2.20 Read Timer
- 5.2.21 Start Timer at T=0
- 5.2.22 Output String with Data
- 5.2.23 Output String Using Character Count
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- 6.1 INTRODUCTION
- 6.2 DIAGNOSTIC MONITOR
- 6.2.1 Monitor Start-Up
- 6.2.2 Command Entry and Directories
- 6.2.3 Help (HE)
- 6.2.4 Self Test (ST)
- 6.2.5 Switch Directories (SD)
- 6.2.6 Loop-On-Error Mode (LE)
- 6.2.7 Stop-On-Error Mode (SE)
- 6.2.8 Loop-Continue Mode (LC)
- 6.2.9 Non-Verbose Mode (NV)
- 6.2.10 Display Error Counters (DE)
- 6.2.11 Clear (Zero) Error Counters (ZE)
- 6.2.12 Display Pass Count (DP)
- 6.2.13 Zero Pass Count (ZP)
- 6.3 UTILITIES
- 6.4 CPU TESTS FOR THE MCU
- 6.5 MEMORY TESTS (MT)
- 6.6 BUS ERROR TEST
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
ASSEMBLER/DISASSEMBLER
M68CPU32BUG/D 4-8
Allowed operators are:
Addition +
Subtraction -
Multiply *
Divide /
Shift left <<
Shift right >>
Bitwise or !
Bitwise and &
The order of evaluation is strictly left to right with no precedence granted to some operators over
others. The only exception is when the user forces the order of precedence via the use of
parentheses.
Possible points of confusion:
• Differentiate numbers and registers to avoid confusion. For example:
CLR D0 means CLR.W register D0. On the other hand,
CLR $D0
CLR 0D0
CLR +D0
CLR D0+0 all mean CLR.W memory location $D0.
• With the use of asterisk (*) to represent both multiply and program counter,
how does the assembler know when to use which definition?
For parsing algebraic expressions, the order of parsing is
<OPERAND> <OPERATOR> <OPERAND> <OPERATOR>
with a possible left or right parenthesis.
Given the above order, the assembler can distinguish by placement which
definition to use. For example:
*** Means PC * PC
*+* Means PC + PC
2** Means 2 * PC
*&&16 Means PC AND &16
ASSEMBLER/DISASSEMBLER
M68CPU32BUG/D 4-9
When specifying operands, the user may skip or omit entries with the following addressing
modes.
• Address register indirect with index, base displacement.
• Program counter indirect with index, base displacement.
For the above modes, the rules for omission/skipping are as follows:
• The user may terminate the operand by specifying ’’)’’.
EXAMPLE
CLR ( ) or
CLR (,,) is equivalent to
CLR (0.N,ZA0,ZD0.W*1)
• The user may skip a field by stepping past it with a comma.
EXAMPLE
CLR (D7) is equivalent to
CLR ($D7,ZA0,ZD0.W*1)
but
CLR (,,D7) is equivalent to
CLR (0.N,ZA0,D7.W*1)
• If the user does not specify the base register, the default is ’’ZA0’’. When Z precedes
the register number, it indicates that register is suppressed.
• If the user does not specify the index register, the default is ’’ZD0.W*1’’.
• Any unspecified displacements are defaulted to ’’0’’.
4.2.3 Define Constant Directive (DC.W)
The format for the DC.W directive is:
DC.W <operand >
This directive defines a constant in memory. The DC.W directive has only one operand (16-bit
value) which can contain the actual value (decimal, hexadecimal, or ASCII). Alternatively, the
operand can be an expression which is assigned a numeric value by the assembler. The constant
is aligned on a word boundary if word (.W) size is specified. An ASCII string is recognized when
characters are enclosed inside single quotes marks (’ . . . ’). Each character (7 bits) is assigned to a
byte of memory with the eighth bit (MSB) always equal to zero. If only one byte is entered, the
byte is right justified. A maximum of two ASCII characters may be entered for each DC.W
directive.
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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