User manual
Table Of Contents
- COVER
- TABLE OF CONTENTS
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
- LIST OF FIGURES
- LIST OF TABLES
- Table 2-1. Debugger Address Parameter Format
- Table 2-2. CPU32Bug Exception Vectors
- Table 3-1. Debug Monitor Commands
- Table 4-1. CPU32Bug Assembler Addressing Modes
- Table 5-1. CPU32Bug System Call Routines
- Table 6-1. MCU CPU Diagnostic Tests
- Table 6-2. Memory Diagnostic Tests
- Table B-1. Self-Test Error Messages
- Table C-1. CPU32Bug Customization Area
- Table C-2. MCU SCI Communication Formats
- Table C-3. Rev. A Chip Selection Summary
- Table C-4. Rev. B Chip Selection Summary
- Table C-5. BCC Rev. C Chip Selection Summary
- Table C-6. PFB Rev. C Compatibility
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- 3.1 INTRODUCTION
- 3.2 BLOCK OF MEMORY COMPARE
- 3.3 BLOCK OF MEMORY FILL
- 3.4 BLOCK OF MEMORY MOVE
- 3.5 BREAKPOINT INSERT/DELETE
- 3.6 BLOCK OF MEMORY SEARCH
- 3.7 BLOCK OF MEMORY VERIFY
- 3.8 DATA CONVERSION
- 3.9 DUMP S-RECORDS
- 3.10 GO DIRECT (IGNORE BREAKPOINTS)
- 3.11 GO TO NEXT INSTRUCTION
- 3.12 GO EXECUTE USER PROGRAM
- 3.13 GO TO TEMPORARY BREAKPOINT
- 3.14 HELP
- 3.15 LOAD S-RECORDS FROM HOST
- 3.16 MACRO DEFINE/DISPLAY/DELETE
- 3.17 MACRO EDIT
- 3.18 MACRO EXPANSION LISTING ENABLE/DISABLE
- 3.19 MEMORY DISPLAY
- 3.20 MEMORY MODIFY
- 3.21 MEMORY SET
- 3.22 OFFSET REGISTERS DISPLAY/MODIFY
- 3.23 PRINTER ATTACH/DETACH
- 3.24 PORT FORMAT
- 3.25 REGISTER DISPLAY
- 3.26 COLD/WARM RESET
- 3.27 REGISTER MODIFY
- 3.28 REGISTER SET
- 3.29 SWITCH DIRECTORIES
- 3.30 TRACE
- 3.31 TRACE ON CHANGE OF CONTROL FLOW
- 3.32 TRANSPARENT MODE
- 3.33 TRACE TO TEMPORARY BREAKPOINT
- 3.34 VERIFY S-RECORDS AGAINST MEMORY
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- 5.1 INTRODUCTION
- 5.2 SYSTEM CALL ROUTINES
- 5.2.1 Calculate BCD Equivalent Specified Binary Number
- 5.2.2 Parse Value, Assign to Variable
- 5.2.3 Check for Break
- 5.2.4 Timer Delay Function
- 5.2.5 Unsigned 32 x 32 Bit Divide
- 5.2.6 Erase Line
- 5.2.7 Input Character Routine
- 5.2.8 Input Line Routine
- 5.2.9 Input Serial Port Status
- 5.2.10 Unsigned 32 x 32 Bit Multiply
- 5.2.11 Output Character Routine
- 5.2.12 Output String Using Pointers
- 5.2.13 Print Carriage Return and Line Feed
- 5.2.14 Read Line to Fixed-Length Buffer
- 5.2.15 Read String Into Variable-Length Buffer
- 5.2.16 Return to CPU32Bug
- 5.2.17 Send Break
- 5.2.18 Compare Two Strings
- 5.2.19 Timer Initialization
- 5.2.20 Read Timer
- 5.2.21 Start Timer at T=0
- 5.2.22 Output String with Data
- 5.2.23 Output String Using Character Count
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- 6.1 INTRODUCTION
- 6.2 DIAGNOSTIC MONITOR
- 6.2.1 Monitor Start-Up
- 6.2.2 Command Entry and Directories
- 6.2.3 Help (HE)
- 6.2.4 Self Test (ST)
- 6.2.5 Switch Directories (SD)
- 6.2.6 Loop-On-Error Mode (LE)
- 6.2.7 Stop-On-Error Mode (SE)
- 6.2.8 Loop-Continue Mode (LC)
- 6.2.9 Non-Verbose Mode (NV)
- 6.2.10 Display Error Counters (DE)
- 6.2.11 Clear (Zero) Error Counters (ZE)
- 6.2.12 Display Pass Count (DP)
- 6.2.13 Zero Pass Count (ZP)
- 6.3 UTILITIES
- 6.4 CPU TESTS FOR THE MCU
- 6.5 MEMORY TESTS (MT)
- 6.6 BUS ERROR TEST
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
ASSEMBLER/DISASSEMBLER
M68CPU32BUG/D 4-4
4.2.1.2 Operand Field
If present, the operand field follows the operation field and is separated from the operation field
by at least one space. When two or more operand subfields appear within a statement, separate
them with a comma. In an instruction like ’ADD D1,D2’, the first subfield (D1) is called the
source effective address (<EA>) field, and the second subfield (D2) is called the destination
<EA> field. Thus, the contents on D1 are added to the contents of D2 and the result saved in
register D2. In the instruction ’MOVE D1,D2’, the first subfield (D1) is the source field and the
second subfield (D2) is the destination field. In other words, for most two-operand instructions,
the format ’<opcode> <source>,<destination>’ applies.
4.2.1.3 Disassembled Source Line
The disassembled source line may not look identical to the source line entered. The disassembler
decides how to interpret the numbers used. If the number is an offset of an address register, it is
treated as a signed hexadecimal offset. Otherwise, it is treated as a straight unsigned
hexadecimal.
EXAMPLE
MOVE.L #1234,5678
MOVE.L FFFFFFFC(A0),5678
disassembles to
00003000 21FC0000 12345678 MOVE.L #$1234,($5678).W
00003008 21E8FFFC 5678 MOVE.L -$4(A0),($5678).W
Also, for some instructions, there are two valid mnemonics for the same opcode, or there is more
than one assembly language equivalent. When the opcode is disassembled some instructions may
appear different from the originally entered code. As examples:
BT is dissembled as BRA
DBRA is dissembled as DBF
NOTE
The assembler recognizes two forms of mnemonics for two branch
instructions. The BT form (branch conditionally true) has the same
opcode as the BRA instruction. Also, DBRA (decrement and
branch always) and DBF (never true, decrement, and branch)
mnemonics are different forms for the same instruction. In each
case, the assembler accepts both forms.
ASSEMBLER/DISASSEMBLER
M68CPU32BUG/D 4-5
4.2.1.4 Mnemonics and Delimiters
The assembler recognizes all M68300 Family instruction mnemonics. Numbers are recognized as
binary, octal, decimal, and hexadecimal, with hexadecimal as the default case.
• Decimal values are preceded by an ampersand (&). Examples are:
&12334
-&987654321
• Hexadecimal values are preceded by a dollar sign ($). An example is:
$AFE5
One or more ASCII characters enclosed by single quote marks ( ’ ) constitute an ASCII string.
ASCII strings are right-justified and zero filled (if necessary), whether stored or used as
immediate operands.
00003000 21FC0000 12345678 MOVE.L #$1234,($5678).W
005000 0053 DC.W ’S’
005002 223C41424344 MOVE.L #’ABCD’,D1
005008 3536 DC.W ’56’
The following register mnemonics are recognized/referenced by the assembler/disassembler:
Pseudo Registers
R0-R7 User Offset Registers.
Main Processor Registers
PC Program Counter - Used only in forcing program counter-relative addressing.
SR Status Register
CCR Condition Codes Register (Lower eight bits of SR)
USP User Stack Pointer
SSP System Stack Pointer
VBR Vector Base Register
SFC Source Function Code Register
DFC Destination Function Code Register
D0-D7 Data Registers
A0-A7 Address Registers - Address register A7 represents the active system stack
pointer, that is, either USP or SSP, as specified by the S bit of the status
register
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