User manual
Table Of Contents
- COVER
- TABLE OF CONTENTS
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
- LIST OF FIGURES
- LIST OF TABLES
- Table 2-1. Debugger Address Parameter Format
- Table 2-2. CPU32Bug Exception Vectors
- Table 3-1. Debug Monitor Commands
- Table 4-1. CPU32Bug Assembler Addressing Modes
- Table 5-1. CPU32Bug System Call Routines
- Table 6-1. MCU CPU Diagnostic Tests
- Table 6-2. Memory Diagnostic Tests
- Table B-1. Self-Test Error Messages
- Table C-1. CPU32Bug Customization Area
- Table C-2. MCU SCI Communication Formats
- Table C-3. Rev. A Chip Selection Summary
- Table C-4. Rev. B Chip Selection Summary
- Table C-5. BCC Rev. C Chip Selection Summary
- Table C-6. PFB Rev. C Compatibility
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- 3.1 INTRODUCTION
- 3.2 BLOCK OF MEMORY COMPARE
- 3.3 BLOCK OF MEMORY FILL
- 3.4 BLOCK OF MEMORY MOVE
- 3.5 BREAKPOINT INSERT/DELETE
- 3.6 BLOCK OF MEMORY SEARCH
- 3.7 BLOCK OF MEMORY VERIFY
- 3.8 DATA CONVERSION
- 3.9 DUMP S-RECORDS
- 3.10 GO DIRECT (IGNORE BREAKPOINTS)
- 3.11 GO TO NEXT INSTRUCTION
- 3.12 GO EXECUTE USER PROGRAM
- 3.13 GO TO TEMPORARY BREAKPOINT
- 3.14 HELP
- 3.15 LOAD S-RECORDS FROM HOST
- 3.16 MACRO DEFINE/DISPLAY/DELETE
- 3.17 MACRO EDIT
- 3.18 MACRO EXPANSION LISTING ENABLE/DISABLE
- 3.19 MEMORY DISPLAY
- 3.20 MEMORY MODIFY
- 3.21 MEMORY SET
- 3.22 OFFSET REGISTERS DISPLAY/MODIFY
- 3.23 PRINTER ATTACH/DETACH
- 3.24 PORT FORMAT
- 3.25 REGISTER DISPLAY
- 3.26 COLD/WARM RESET
- 3.27 REGISTER MODIFY
- 3.28 REGISTER SET
- 3.29 SWITCH DIRECTORIES
- 3.30 TRACE
- 3.31 TRACE ON CHANGE OF CONTROL FLOW
- 3.32 TRANSPARENT MODE
- 3.33 TRACE TO TEMPORARY BREAKPOINT
- 3.34 VERIFY S-RECORDS AGAINST MEMORY
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- 5.1 INTRODUCTION
- 5.2 SYSTEM CALL ROUTINES
- 5.2.1 Calculate BCD Equivalent Specified Binary Number
- 5.2.2 Parse Value, Assign to Variable
- 5.2.3 Check for Break
- 5.2.4 Timer Delay Function
- 5.2.5 Unsigned 32 x 32 Bit Divide
- 5.2.6 Erase Line
- 5.2.7 Input Character Routine
- 5.2.8 Input Line Routine
- 5.2.9 Input Serial Port Status
- 5.2.10 Unsigned 32 x 32 Bit Multiply
- 5.2.11 Output Character Routine
- 5.2.12 Output String Using Pointers
- 5.2.13 Print Carriage Return and Line Feed
- 5.2.14 Read Line to Fixed-Length Buffer
- 5.2.15 Read String Into Variable-Length Buffer
- 5.2.16 Return to CPU32Bug
- 5.2.17 Send Break
- 5.2.18 Compare Two Strings
- 5.2.19 Timer Initialization
- 5.2.20 Read Timer
- 5.2.21 Start Timer at T=0
- 5.2.22 Output String with Data
- 5.2.23 Output String Using Character Count
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- 6.1 INTRODUCTION
- 6.2 DIAGNOSTIC MONITOR
- 6.2.1 Monitor Start-Up
- 6.2.2 Command Entry and Directories
- 6.2.3 Help (HE)
- 6.2.4 Self Test (ST)
- 6.2.5 Switch Directories (SD)
- 6.2.6 Loop-On-Error Mode (LE)
- 6.2.7 Stop-On-Error Mode (SE)
- 6.2.8 Loop-Continue Mode (LC)
- 6.2.9 Non-Verbose Mode (NV)
- 6.2.10 Display Error Counters (DE)
- 6.2.11 Clear (Zero) Error Counters (ZE)
- 6.2.12 Display Pass Count (DP)
- 6.2.13 Zero Pass Count (ZP)
- 6.3 UTILITIES
- 6.4 CPU TESTS FOR THE MCU
- 6.5 MEMORY TESTS (MT)
- 6.6 BUS ERROR TEST
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION

DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-46
OF Offset Registers Display/Modify OF
Offset register rules:
• At power-up and cold-start reset, R7 is the automatic register, and all offset registers
have both base and top addresses preset to 0. This disables the offset registers.
• R7 always has both base and top addresses set to 0; it cannot be changed.
• Any offset register can be set as the automatic register.
• The automatic register is always added to every absolute address argument of every
CPU32Bug command where an offset register is not explicitly defined (this includes
the OF command itself). To enter an absolute address, always add R7 to the address,
i.e. +R7.
• The register commands (RD, RM) do not use the automatic register, i.e. the program
counter is always displayed/entered absolutely. However, the RS (register set)
command does use the automatic register.
• There is always an automatic register. To disable the effect of the automatic register
set R7 as the automatic register. This is the default condition.
EXAMPLES Display offset registers. Shows base and top values for each register.
CPU32Bug>OF<CR>
R0 = 00000000 00000000 R1 = 00000000 00000000
R2 = 00000000 00000000 R3 = 00000000 00000000
R4 = 00000000 00000000 R5 = 00000000 00000000
R6 = 00000000 00000000 R7*= 00000000 00000000
Modify offset registers.
CPU32Bug>OF R0<CR>
R0 = 00000000 00000000? 5000 50FF<CR>
R1 = 00000000 00000000? 5100:200^<CR>
Modify and backup
R0 = 00020000 000200FF? <CR> No change, backup still utilized
R6 = 00000000 00000000? .<CR> Exit. Notice wrap around to R6.
Display location $5000. Shows base and top values for each register.
CPU32Bug>M 5000;DI<CR>
00000+R0 41F95445 5354 LEA.L ($54455354).L,A0 .<CR>
CPU32Bug>M R0;DI <CR>
00000+R0 41F95445 5354 LEA.L ($54455354).L,A0 .<CR>
CPU32Bug>
DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-43
MM Memory Modify MM
EXAMPLES
CPU32Bug>MM 3100<CR> Access location 3100.
00003100 1234?<CR>
00003102 5678? 4321<CR> Modify memory.
00003104 9ABC? 8765^<CR> Modify memory and backup.
00003102 4321?<CR> No change, backup still utilized.
00003100 1234? abcd.<CR> Modify memory and exit.
CPU32Bug>MM 3001;LA<CR> Longword access to location 3001.
00003001 CD432187?<CR> Alternate location accesses.
00003009 00068010? 68010+10=<CR> Modify and re-open location.
00003009 00068020?<CR> No change, re-open still utilized.
00003009 00068020? .<CR> Exit MM.
CPU32Bug>MM 4000<CR> Modify WORDs starting at $4000.
00004000 0000? ’A’<CR> Enter ASCII ’A’, right justified.
00004002 0000? ’B’<CR> Enter ASCII ’B’, right justified.
00004004 0000? ’CD’<CR> Enter ASCII ’CD’, right justified.
00004006 0000? ’EFG’<CR> Enter ASCII ’FG’, right justified. Note the ’E’ is
truncated due to right justified WORD size!
00004008 0000? .<CR> Exit MM.
CPU32Bug>MD 4000<CR>
00004008 0041 0042 4344 4647 0000 0000 0000 0000 .A.BCDFG........
CPU32Bug>
The DI option activates the one-line assembler/disassembler. All other options are invalid if DI is
selected. The contents of the specified memory location is disassembled and displayed and the
user prompted for an input with a question mark ( ? ). At this point the user has three options:
• Enter <CR> – This closes the present location and continues with disassembly of the
next instruction. The instruction is unchanged.
• Enter a new source instruction followed by <CR> – This actuates the assembler to
assemble the new instruction and generate a disassembly of the object code generated.
• Enter <CR> – This closes the present location and exits the MM command.
If a new source line is entered (second option above), the present line is erased and replaced by
the new source line.
If an error is found during assembly, the caret symbol (^) appears below the suspect field
followed by an error message. The accessed location is redisplayed.
Refer to Chapter 4 for additional information about the assembler.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
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