User manual
Table Of Contents
- COVER
- TABLE OF CONTENTS
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
- LIST OF FIGURES
- LIST OF TABLES
- Table 2-1. Debugger Address Parameter Format
- Table 2-2. CPU32Bug Exception Vectors
- Table 3-1. Debug Monitor Commands
- Table 4-1. CPU32Bug Assembler Addressing Modes
- Table 5-1. CPU32Bug System Call Routines
- Table 6-1. MCU CPU Diagnostic Tests
- Table 6-2. Memory Diagnostic Tests
- Table B-1. Self-Test Error Messages
- Table C-1. CPU32Bug Customization Area
- Table C-2. MCU SCI Communication Formats
- Table C-3. Rev. A Chip Selection Summary
- Table C-4. Rev. B Chip Selection Summary
- Table C-5. BCC Rev. C Chip Selection Summary
- Table C-6. PFB Rev. C Compatibility
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- 3.1 INTRODUCTION
- 3.2 BLOCK OF MEMORY COMPARE
- 3.3 BLOCK OF MEMORY FILL
- 3.4 BLOCK OF MEMORY MOVE
- 3.5 BREAKPOINT INSERT/DELETE
- 3.6 BLOCK OF MEMORY SEARCH
- 3.7 BLOCK OF MEMORY VERIFY
- 3.8 DATA CONVERSION
- 3.9 DUMP S-RECORDS
- 3.10 GO DIRECT (IGNORE BREAKPOINTS)
- 3.11 GO TO NEXT INSTRUCTION
- 3.12 GO EXECUTE USER PROGRAM
- 3.13 GO TO TEMPORARY BREAKPOINT
- 3.14 HELP
- 3.15 LOAD S-RECORDS FROM HOST
- 3.16 MACRO DEFINE/DISPLAY/DELETE
- 3.17 MACRO EDIT
- 3.18 MACRO EXPANSION LISTING ENABLE/DISABLE
- 3.19 MEMORY DISPLAY
- 3.20 MEMORY MODIFY
- 3.21 MEMORY SET
- 3.22 OFFSET REGISTERS DISPLAY/MODIFY
- 3.23 PRINTER ATTACH/DETACH
- 3.24 PORT FORMAT
- 3.25 REGISTER DISPLAY
- 3.26 COLD/WARM RESET
- 3.27 REGISTER MODIFY
- 3.28 REGISTER SET
- 3.29 SWITCH DIRECTORIES
- 3.30 TRACE
- 3.31 TRACE ON CHANGE OF CONTROL FLOW
- 3.32 TRANSPARENT MODE
- 3.33 TRACE TO TEMPORARY BREAKPOINT
- 3.34 VERIFY S-RECORDS AGAINST MEMORY
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- 5.1 INTRODUCTION
- 5.2 SYSTEM CALL ROUTINES
- 5.2.1 Calculate BCD Equivalent Specified Binary Number
- 5.2.2 Parse Value, Assign to Variable
- 5.2.3 Check for Break
- 5.2.4 Timer Delay Function
- 5.2.5 Unsigned 32 x 32 Bit Divide
- 5.2.6 Erase Line
- 5.2.7 Input Character Routine
- 5.2.8 Input Line Routine
- 5.2.9 Input Serial Port Status
- 5.2.10 Unsigned 32 x 32 Bit Multiply
- 5.2.11 Output Character Routine
- 5.2.12 Output String Using Pointers
- 5.2.13 Print Carriage Return and Line Feed
- 5.2.14 Read Line to Fixed-Length Buffer
- 5.2.15 Read String Into Variable-Length Buffer
- 5.2.16 Return to CPU32Bug
- 5.2.17 Send Break
- 5.2.18 Compare Two Strings
- 5.2.19 Timer Initialization
- 5.2.20 Read Timer
- 5.2.21 Start Timer at T=0
- 5.2.22 Output String with Data
- 5.2.23 Output String Using Character Count
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- 6.1 INTRODUCTION
- 6.2 DIAGNOSTIC MONITOR
- 6.2.1 Monitor Start-Up
- 6.2.2 Command Entry and Directories
- 6.2.3 Help (HE)
- 6.2.4 Self Test (ST)
- 6.2.5 Switch Directories (SD)
- 6.2.6 Loop-On-Error Mode (LE)
- 6.2.7 Stop-On-Error Mode (SE)
- 6.2.8 Loop-Continue Mode (LC)
- 6.2.9 Non-Verbose Mode (NV)
- 6.2.10 Display Error Counters (DE)
- 6.2.11 Clear (Zero) Error Counters (ZE)
- 6.2.12 Display Pass Count (DP)
- 6.2.13 Zero Pass Count (ZP)
- 6.3 UTILITIES
- 6.4 CPU TESTS FOR THE MCU
- 6.5 MEMORY TESTS (MT)
- 6.6 BUS ERROR TEST
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-26
GT Go To Temporary Breakpoint GT
3.13 GO TO TEMPORARY BREAKPOINT
GT <addr>[:<count>]
Use the GT command to set a temporary breakpoint and start target code execution. A count may
be specified with the temporary breakpoint. Control is given at the target PC address. All
previously set breakpoints are enabled. The temporary breakpoint is removed when any
breakpoint with 0 count is encountered.
After setting the temporary breakpoint, the sequence of events is similar to that of the GO
command. At this point control is returned to CPU32Bug by:
• Executing the .RETURN SYSCALL (TRAP #15) function
• Press the ABORT switch or RESET switch of the M68300PFB Platform Board
• Encountering a breakpoint with 0 count
• Generation of an unexpected exception
EXAMPLE The following program resides at $4000.
CPU32Bug>MD 4000;DI<CR>
00004000 2200 MOVE.L D0,D1
00004002 4282 CLR.L D2
00004004 D401 ADD.B D1,D2
00004006 E289 LSR.L #$1,D1
00004008 66FA BNE.B $4004
0000400A E20A LSR.B #$1,D2
0000400C 55C2 SCS D2
0000400E 60FE BRA.B $400E
CPU32Bug>RM D0<CR>
Initialize D0 and set a breakpoint:
D0 =00000000 ? 52A9C.<CR>
CPU32Bug>BR 400E<CR>
BREAKFOINTS
0000400E
CPU32Bug>
Set PC to beginning of program, set temporary breakpoint, and start target code:
CPU32Bug>RM PC<CR>
PC =0000400E ? 4000.<CR>
CPU32Bug>
DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-23
GO Go Execute User Program GO
3.12 GO EXECUTE USER PROGRAM
GO [<addr>]
Use the GO command (alias G) to initiate target code execution. All previously set breakpoints
are enabled. If an address is specified, it is placed in the target PC. Execution starts at the target
PC address.
The sequence of events is:
1. An address is specified and loaded into the target PC
2. If a breakpoint is set at the target PC address, the instruction is traced at the target PC
(executed in trace mode)
3. All breakpoints are inserted in the target code
4. Target code execution resumes at the target PC address
There are several methods for returning control to CPU32Bug:
• Execute the .RETURN TRAP #15 function
• Press the ABORT switch or RESET switch of the M68300PFB Platform Board
• Encountering a breakpoint with 0 count
• Generation of an unexpected exception
EXAMPLE The following program resides at $4000.
CPU32Bug>MD 4000;DI<CR>
00004000 2200 MOVE.L D0,D1
00004002 4282 CLR.L D2
00004004 D401 ADD.B D1,D2
00004006 E289 LSR.L #$1,D1
00004008 66FA BNE.B $4004
0000400A E20A LSR.B #$1,D2
0000400C 55C2 SCS.B D2
0000400E 60FE BRA.B $400E
CPU32Bug>RM D0<CR>
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eescale S
emiconduct
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Freescale Semiconductor, Inc.
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