User manual
Table Of Contents
- COVER
- TABLE OF CONTENTS
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
- LIST OF FIGURES
- LIST OF TABLES
- Table 2-1. Debugger Address Parameter Format
- Table 2-2. CPU32Bug Exception Vectors
- Table 3-1. Debug Monitor Commands
- Table 4-1. CPU32Bug Assembler Addressing Modes
- Table 5-1. CPU32Bug System Call Routines
- Table 6-1. MCU CPU Diagnostic Tests
- Table 6-2. Memory Diagnostic Tests
- Table B-1. Self-Test Error Messages
- Table C-1. CPU32Bug Customization Area
- Table C-2. MCU SCI Communication Formats
- Table C-3. Rev. A Chip Selection Summary
- Table C-4. Rev. B Chip Selection Summary
- Table C-5. BCC Rev. C Chip Selection Summary
- Table C-6. PFB Rev. C Compatibility
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- 3.1 INTRODUCTION
- 3.2 BLOCK OF MEMORY COMPARE
- 3.3 BLOCK OF MEMORY FILL
- 3.4 BLOCK OF MEMORY MOVE
- 3.5 BREAKPOINT INSERT/DELETE
- 3.6 BLOCK OF MEMORY SEARCH
- 3.7 BLOCK OF MEMORY VERIFY
- 3.8 DATA CONVERSION
- 3.9 DUMP S-RECORDS
- 3.10 GO DIRECT (IGNORE BREAKPOINTS)
- 3.11 GO TO NEXT INSTRUCTION
- 3.12 GO EXECUTE USER PROGRAM
- 3.13 GO TO TEMPORARY BREAKPOINT
- 3.14 HELP
- 3.15 LOAD S-RECORDS FROM HOST
- 3.16 MACRO DEFINE/DISPLAY/DELETE
- 3.17 MACRO EDIT
- 3.18 MACRO EXPANSION LISTING ENABLE/DISABLE
- 3.19 MEMORY DISPLAY
- 3.20 MEMORY MODIFY
- 3.21 MEMORY SET
- 3.22 OFFSET REGISTERS DISPLAY/MODIFY
- 3.23 PRINTER ATTACH/DETACH
- 3.24 PORT FORMAT
- 3.25 REGISTER DISPLAY
- 3.26 COLD/WARM RESET
- 3.27 REGISTER MODIFY
- 3.28 REGISTER SET
- 3.29 SWITCH DIRECTORIES
- 3.30 TRACE
- 3.31 TRACE ON CHANGE OF CONTROL FLOW
- 3.32 TRANSPARENT MODE
- 3.33 TRACE TO TEMPORARY BREAKPOINT
- 3.34 VERIFY S-RECORDS AGAINST MEMORY
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- 5.1 INTRODUCTION
- 5.2 SYSTEM CALL ROUTINES
- 5.2.1 Calculate BCD Equivalent Specified Binary Number
- 5.2.2 Parse Value, Assign to Variable
- 5.2.3 Check for Break
- 5.2.4 Timer Delay Function
- 5.2.5 Unsigned 32 x 32 Bit Divide
- 5.2.6 Erase Line
- 5.2.7 Input Character Routine
- 5.2.8 Input Line Routine
- 5.2.9 Input Serial Port Status
- 5.2.10 Unsigned 32 x 32 Bit Multiply
- 5.2.11 Output Character Routine
- 5.2.12 Output String Using Pointers
- 5.2.13 Print Carriage Return and Line Feed
- 5.2.14 Read Line to Fixed-Length Buffer
- 5.2.15 Read String Into Variable-Length Buffer
- 5.2.16 Return to CPU32Bug
- 5.2.17 Send Break
- 5.2.18 Compare Two Strings
- 5.2.19 Timer Initialization
- 5.2.20 Read Timer
- 5.2.21 Start Timer at T=0
- 5.2.22 Output String with Data
- 5.2.23 Output String Using Character Count
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- 6.1 INTRODUCTION
- 6.2 DIAGNOSTIC MONITOR
- 6.2.1 Monitor Start-Up
- 6.2.2 Command Entry and Directories
- 6.2.3 Help (HE)
- 6.2.4 Self Test (ST)
- 6.2.5 Switch Directories (SD)
- 6.2.6 Loop-On-Error Mode (LE)
- 6.2.7 Stop-On-Error Mode (SE)
- 6.2.8 Loop-Continue Mode (LC)
- 6.2.9 Non-Verbose Mode (NV)
- 6.2.10 Display Error Counters (DE)
- 6.2.11 Clear (Zero) Error Counters (ZE)
- 6.2.12 Display Pass Count (DP)
- 6.2.13 Zero Pass Count (ZP)
- 6.3 UTILITIES
- 6.4 CPU TESTS FOR THE MCU
- 6.5 MEMORY TESTS (MT)
- 6.6 BUS ERROR TEST
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-6
BF Block of Memory Fill BF
CPU32Bug>BF 4000:10 4E71 ;B<CR>
Effective address: 00004000
Effective count : &16
Truncated data = $71
CPU32Bug>MD 4000:30;B<CR>
00004000 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 qqqqqqqqqqqqqqqq
00004010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00004020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
CPU32Bug>
The specified data did not fit into the specified data field size. The data was truncated and the
’’Data = ’’ message was output.
CPU32Bug>BF 4000,4006 12345678 ;L<CR>
Effective address: 00004000
Effective address: 00004003
CPU32Bug>MD 4000:30;B<CR>
00004000 12 34 56 78 00 00 00 00 00 00 00 00 00 00 00 00 .4Vx............
00004010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
00004020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
CPU32Bug>
The longword pattern would not fit evenly in the given range. Only one longword was written
and the ’’Effective address’’ messages reflect the fact that data was not written all the way up to
the specified address.
CPU32Bug>BF 4000:18 0 1<CR> Default size is Word
Effective address: 00004000
Effective count : &24
CPU32Bug>MD 4000:18<CR>
00004000 0000 0001 0002 0003 0004 0005 0006 0007 ................
00004010 0008 0009 000A 000B 000C 000D 000E 000F ................
00004020 0010 0011 0012 0013 0014 0015 0016 0017 ................
DEBUG MONITOR COMMANDS
M68CPU32BUG/D REV 1 3-3
BC Block of Memory Compare BC
3.2 BLOCK OF MEMORY COMPARE
BC <range><del><addr>[;B|W|L]
options:
B – Byte
W – Word
L – Longword
The BC command compares the contents of the memory addresses defined by <range> to another
place in memory, beginning at <addr>.
The option field is only allowed when <range> is specified using a count. In this case, the B, W,
or L defines the size of data to which the count is referring. For example, a count of four with an
option of L would mean to compare four long words (or 16 bytes) to the <addr> location. If the
range beginning address is greater than the end address, an error results. An error also results if
an option field is specified without a count in the range.
For the following examples, assume the following data is in memory.
CPU32Bug>MD 4000:20;B<CR>
00004000 54 48 49 53 20 49 53 20 41 20 54 45 53 54 21 21 THIS IS A TEST!!
00004010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
CPU32Bug>MD 4100:20;B<CR>
00004100 54 48 49 53 20 49 53 20 41 20 54 45 53 54 21 21 THIS IS A TEST!!
00004110 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
EXAMPLES
CPU32Bug>BC 4000,401F 4100<CR>
Effective address: 00004000
Effective address: 0000401F
Effective address: 00004100
CPU32Bug> Memory compares, nothing printed
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eescale S
emiconduct
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