User manual
Table Of Contents
- COVER
- TABLE OF CONTENTS
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
- LIST OF FIGURES
- LIST OF TABLES
- Table 2-1. Debugger Address Parameter Format
- Table 2-2. CPU32Bug Exception Vectors
- Table 3-1. Debug Monitor Commands
- Table 4-1. CPU32Bug Assembler Addressing Modes
- Table 5-1. CPU32Bug System Call Routines
- Table 6-1. MCU CPU Diagnostic Tests
- Table 6-2. Memory Diagnostic Tests
- Table B-1. Self-Test Error Messages
- Table C-1. CPU32Bug Customization Area
- Table C-2. MCU SCI Communication Formats
- Table C-3. Rev. A Chip Selection Summary
- Table C-4. Rev. B Chip Selection Summary
- Table C-5. BCC Rev. C Chip Selection Summary
- Table C-6. PFB Rev. C Compatibility
- CHAPTER 1 GENERAL INFORMATION
- CHAPTER 2 DEBUG MONITOR DESCRIPTION
- CHAPTER 3 DEBUG MONITOR COMMANDS
- 3.1 INTRODUCTION
- 3.2 BLOCK OF MEMORY COMPARE
- 3.3 BLOCK OF MEMORY FILL
- 3.4 BLOCK OF MEMORY MOVE
- 3.5 BREAKPOINT INSERT/DELETE
- 3.6 BLOCK OF MEMORY SEARCH
- 3.7 BLOCK OF MEMORY VERIFY
- 3.8 DATA CONVERSION
- 3.9 DUMP S-RECORDS
- 3.10 GO DIRECT (IGNORE BREAKPOINTS)
- 3.11 GO TO NEXT INSTRUCTION
- 3.12 GO EXECUTE USER PROGRAM
- 3.13 GO TO TEMPORARY BREAKPOINT
- 3.14 HELP
- 3.15 LOAD S-RECORDS FROM HOST
- 3.16 MACRO DEFINE/DISPLAY/DELETE
- 3.17 MACRO EDIT
- 3.18 MACRO EXPANSION LISTING ENABLE/DISABLE
- 3.19 MEMORY DISPLAY
- 3.20 MEMORY MODIFY
- 3.21 MEMORY SET
- 3.22 OFFSET REGISTERS DISPLAY/MODIFY
- 3.23 PRINTER ATTACH/DETACH
- 3.24 PORT FORMAT
- 3.25 REGISTER DISPLAY
- 3.26 COLD/WARM RESET
- 3.27 REGISTER MODIFY
- 3.28 REGISTER SET
- 3.29 SWITCH DIRECTORIES
- 3.30 TRACE
- 3.31 TRACE ON CHANGE OF CONTROL FLOW
- 3.32 TRANSPARENT MODE
- 3.33 TRACE TO TEMPORARY BREAKPOINT
- 3.34 VERIFY S-RECORDS AGAINST MEMORY
- CHAPTER 4 ASSEMBLER/DISASSEMBLER
- CHAPTER 5 SYSTEM CALLS
- 5.1 INTRODUCTION
- 5.2 SYSTEM CALL ROUTINES
- 5.2.1 Calculate BCD Equivalent Specified Binary Number
- 5.2.2 Parse Value, Assign to Variable
- 5.2.3 Check for Break
- 5.2.4 Timer Delay Function
- 5.2.5 Unsigned 32 x 32 Bit Divide
- 5.2.6 Erase Line
- 5.2.7 Input Character Routine
- 5.2.8 Input Line Routine
- 5.2.9 Input Serial Port Status
- 5.2.10 Unsigned 32 x 32 Bit Multiply
- 5.2.11 Output Character Routine
- 5.2.12 Output String Using Pointers
- 5.2.13 Print Carriage Return and Line Feed
- 5.2.14 Read Line to Fixed-Length Buffer
- 5.2.15 Read String Into Variable-Length Buffer
- 5.2.16 Return to CPU32Bug
- 5.2.17 Send Break
- 5.2.18 Compare Two Strings
- 5.2.19 Timer Initialization
- 5.2.20 Read Timer
- 5.2.21 Start Timer at T=0
- 5.2.22 Output String with Data
- 5.2.23 Output String Using Character Count
- CHAPTER 6 DIAGNOSTIC FIRMWARE GUIDE
- 6.1 INTRODUCTION
- 6.2 DIAGNOSTIC MONITOR
- 6.2.1 Monitor Start-Up
- 6.2.2 Command Entry and Directories
- 6.2.3 Help (HE)
- 6.2.4 Self Test (ST)
- 6.2.5 Switch Directories (SD)
- 6.2.6 Loop-On-Error Mode (LE)
- 6.2.7 Stop-On-Error Mode (SE)
- 6.2.8 Loop-Continue Mode (LC)
- 6.2.9 Non-Verbose Mode (NV)
- 6.2.10 Display Error Counters (DE)
- 6.2.11 Clear (Zero) Error Counters (ZE)
- 6.2.12 Display Pass Count (DP)
- 6.2.13 Zero Pass Count (ZP)
- 6.3 UTILITIES
- 6.4 CPU TESTS FOR THE MCU
- 6.5 MEMORY TESTS (MT)
- 6.6 BUS ERROR TEST
- APPENDIX A S-RECORD INFORMATION
- APPENDIX B SELF-TEST ERROR MESSAGES
- APPENDIX C USER CUSTOMIZATION
DEBUG MONITOR DESCRIPTION
M68CPU32BUG/D REV 1 2-12
Before the normal register display information is printed, the exception type information is
displayed. This includes the type of exception with its format/vector word and the following:
Mnemonic Description Offset
SSW Special Status Word +$16
Fault Addr. Faulted Address +$10
Data Data +$0C
Cur. PC Program Counter +$02
Cnt. Reg. Internal Transfer
Count Register
+$14
The upper nibble of the count register (Cnt. Reg.) contains the microcode revision number of the
MCU device. Consult the CPU32 Reference Manual, Section 6 Exception Processing for more
details.
Notice that the target stack pointer is different. The target stack pointer now points to the last
value of the stacked exception stack frame. Examine the exception stack frame using the MD
command.
CPU32Bug>MD (A7):C<CR>
00003FE8 A700 0000 3000 C008 00F0 0000 FFFF 3000 ‘...0.@ p....0.
00003FF8 0000 3000 0001 0065 ..0....e
CPU32Bug>
2.6 FUNCTION CODE SUPPORT
Function codes identify the address space being accessed on any given bus cycle, and are an
extension of the address. The function codes provide additional information required to find the
proper memory location.
For this reason, all debugger commands involving an address field were changed to allow the
specification of function codes:
The caret ( ^ ) symbol following the address field indicates that a function code specification
follows. The function code can be entered by specifying a valid function code mnemonic or by
specifying a number between 0 and 7. The syntax for address and function code specifications
are:
<ADDR>^<FC> Sets the function code to <FC> value.
<ADDR>^^ Toggles the displaying of function code values.
<ADDR>^<FC>= Sets the function code to <FC> and the default function code to <FC>.
The default value at power up is SD.
DEBUG MONITOR DESCRIPTION
M68CPU32BUG/D REV 1 2-9
EXAMPLE Trace one instruction using debugger.
CPU32Bug>RD<CR>
PC =00003000 SR =2700=TR:OFF_S_7_..... VBR =00000000
SFC =5=SD DFC =5=SD USP =00003830 SSP* =00004000
D0 =00000000 D1 =00000000 D2 =00000000 D3 =00000000
D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000
A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000
A4 =00000000 A5 =00000000 A6 =00000000 A7 =00004000
00003000 203900100000 MOVE.L ($100000).L,D0
CPU32Bug>T<CR>
PC =00003006 SR =2700=TR:OFF_S_7_..... VBR =00000000
SFC =5=SD DFC =5=SD USP =00003830 SSP* =00004000
D0 =12345678 D1 =00000000 D2 =00000000 D3 =00000000
D4 =00000000 D5 =00000000 D6 =00000000 D7 =00000000
A0 =00000000 A1 =00000000 A2 =00000000 A3 =00000000
A4 =00000000 A5 =00000000 A6 =00000000 A7 =00004000
00003006 D280 ADD.L D0,D1
CPU32Bug>
Notice that the value of the target stack pointer register (A7) has not changed even though a trace
exception has taken place. The user program may use the exception vector table provided by
CPU32Bug or it may create a separate exception vector table of its own.
2.5.2.1 Using CPU32Bug Target Vector Table
CPU32Bug initializes and maintains a vector table area for target programs. A target program is
any user program started by the CPU32Bug with GO or Trace commands. The starting address of
this target-vector table area is the base address of the BCC, described in paragraph 1.6. This
address is loaded into the target-state-vector base register at power-up or during a cold-start reset.
For verification use the RD command immediately after power-up to display the target-state
registers.
CPU32Bug loads the target-vector table with the debugger vectors (listed in Table 2-2) and the
other vector locations with the address of a generalized exception handler (refer to paragraph
2.5.2.3). The target program allocates as many vectors as required by simply writing its own
exception vectors into the table. If the vector locations listed in Table 2-2 are over-written, then
the accompanying debugger functions will be lost.
CPU32Bug maintains a separate vector table for its own use in a 1k byte space in the reserved
memory space. The debugger vector table is completely transparent to the user and no
modifications should ever be made to it.
Fr
eescale S
emiconduct
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Freescale Semiconductor, Inc.
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