User`s manual

MOTOROLA MC68332TUT/D
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4 ∗ $84 + $00 = $210
Thus, the starting address of the interrupt routine must be stored in location $210.
2. Store an interrupt priority level for the TPU in bits 10 through 8 of the TICR.
A. This value determines the priority of TPU interrupt service requests. The value must be a number
between 1 and 7— level 7 has the highest priority, and level 1 has the lowest. The value stored
in the IPL field in the CPU status register determines whether an interrupt request is recognized.
The value in the IPL field must be lower than the TPU interrupt priority level in order for the TPU
to interrupt the CPU, unless the interrupt level is seven, in which case it cannot be masked.
3. Store an interrupt arbitration value in the IARB field of the TPU module configuration register.
A. The IARB field value determines precedence when the CPU receives more than one interrupt re-
quest of the same interrupt priority level. Each interrupting module must be assigned a unique
IARB number between $01 (lowest precedence) and $0F (highest precedence).
4. Set the interrupt enable bit for the channel in the channel interrupt enable register (CIER). This simply
involves writing the channel's bit number to a one.
To clear an interrupt, negate the appropriate interrupt status flag in the channel interrupt status register
(CISR). Read the flag in the asserted state and then write a zero to the bit. As long as the CISR bit is set,
the channel will continue to request interrupts.
4.5.4 TPU Initialization Examples
The following example initializes channel 0 to run the PWM function. The output of channel 0 will be a 50%
duty cycle square wave. The frequency will be (SYSCLK/4)/$4000. For 16.778 MHz, this is (4194500/
16384) = 256 Hz. It assumes that the “MM” bit in the SIMCR is set to a one.
SYNCR EQU $FFFA04
SYPCR EQU $FFFA21
CFSR3 EQU $FFFE12
TPUMCR EQU $FFFE00
HSQR1 EQU $FFFE16
HSSR1 EQU $FFFE1A
CPR1 EQU $FFFE1E
ORG $400 ;begin program at $400, immediately
;after the exception table
INITSYS:
MOVE.B #$7F,(SYNCR).L ;set system clock to 16.78 MHz
CLR.B (SYPCR).L ;disable software watchdog
CNTLREG:
MOVE.W #$0009,(CFSR3).L ;channel function select field. Note:
;function numbers may vary with differ-
;ent mask sets.
MOVE.W #$00C0,(TPUMCR).L ;set TCR1 to SYSCLK/4. At 16.778 MHz,
;this means that 1 TCR1 count = 238nsec.
MOVE.W #$0000,(HSQR1).L ;HSQ bits = 0 for PWM function
PRAM:
MOVE.W #$0092,($FFFF00).L ;Channel Control Reg: Force pin low at
;initialization, use TCR1
MOVE.W #$2000,($FFFF04).L ;High time = $2000 TCR1 counts
MOVE.W #$4000,($FFFF06).L ;Period = $4000 TCR1 counts
START:
MOVE.W #$0002,(HSSR1).L ;Host service request for initialization
MOVE.W #$0003,(CPR1).L ;Give channel high priority
DONE BRA DONE
Following is a short example that generates interrupts on Channel 4: