User`s manual
MOTOROLA MC68332TUT/D
40
;state of SCK as low, capture data on the
;leading edge of SCK, baud rate is 4.19 MHz
;The BITS filed is a don’t-care value because
;the BITSE filed is cleared, thus selecting
;8 data bits per transmission.
* The next command sets the control parameters. Interrupts are not enabled. To
* enable interrupts upon assertion of the SPIF bit, set SPCR2[15]. To clear
* an interrupt, read and then clear the SPIF bit. Wrap-around mode is enabled.
* NEWQP is set to zero, and ENDQP is set to $F. Thus, the QSPI will
* continuously transmit the data between $0 and $F in the queue. To disable
* wrap-around mode so that the QSPI only goes through the queue once, clear the
* WREN bit (SPCR2[14]) to a zero.
MOVE.W #$4F00,(SPCR2).L
MOVE.B #$00,(SPCR3).L ;Disable loop mode, HALTA and MODF
;interrupts, and HALT.
MOVEA.L #DATA,A0 ;Point A0 to the address of the data to be
;transmitted.
MOVEA.L #TXDRAM,A1 ;Point A1 to the transmit data RAM.
MOVEA.L #CMDRAM,A2 ;Point A2 to the command RAM
MOVE.W #$10,D0 ;Set a counter to count down from 16 ($10),
;since there are 16 queue entries to fill.
CLR.L D1 ;Clear D1. It will be used to fill the
;transmit RAM.
LOOP MOVE.B (A0)+,D1 ;Begin a loop to fill the transmit RAM.
MOVE.W D1,(A1)+ ;Store the data right-justified.
* The next command fills the command RAM in a right-justified manner. There is
* one byte of control information for each QSPI command to be executed in the
* queue. Here, 8 bits of data are transmitted, and all four peripheral
* chip-select signals are configured to drive low.
MOVE.B #$00,(A2)+
SUBI.W #$01,D0 ;Subtract one from the counter
BNE LOOP ;Fill next queue entry if not done
MOVE.W #$8000,(SPCR1).L ;Begin operation by setting the SPE bit.
;This is the last step of initialization.
FINISH
BRA FINISH ;Normally, this would begin the next task.
DATA DB 16 ;Set aside memory space for the data to be
;transmitted. This program does not
;initialize the data.
4.4.3 Initializing QSM Interrupts
To enable interrupts on the QSM, initialize the following five fields:
1. ILQSPI and ILSCI in the QILR register determine the priority levels of QSPI and SCI interrupts, re-
spectively. If the fields are set to the same level, the QSPI takes priority.
2. INTV[7:0] in the QIVR register determines the interrupt vector number. For the QSPI, the least sig-
nificant bit is read as a one, and for the SCI, the least significant bit is read as a zero.
3. IARB in the QSMCR register determines precedence if the QSM and another module simultaneously
make an interrupt service request of the same priority. This field must be initialized to a unique, non-
zero value if interrupts are enabled.
4. IPL in the CPU status register determines the priority level at which interrupts are recognized. In order
for QSM interrupts to be recognized, this field must be given a value that is lower than the interrupt
priority level specified in the QILR register.
5. The interrupt vector tells the processor where to find the interrupt service routine. Store the starting
address of the service routine in the interrupt vector table at the appropriate vector offset address.
The vector offset address is equal to (interrupt vector number X 4) + address stored in the VBR.