User`s manual

MC68332TUT/D MOTOROLA

4.2.5 Periodic Interrupt Control Register (PICR)

1. Determine the appropriate PIT vector number and interrupt priority.

2. Write vector number and interrupt priority to PIV and PIRQL fields in PICR.

4.2.6 Chip-Select Pin Assignment Registers (CSPAR0 and CSPAR1)

The chip-select pins can be used in a number of ways. CSPAR determine the functions of the pins.

1. Set up the chip-select pins for discrete output, 8-bit chip-select operation, 16-bit chip-select operation,

or alternate function.

2. If a chip-select circuit is used to generate an interrupt acknowledge signal, it must be configured for

chip-select operation. However, if a chip-select circuit is used to generate an autovector, the pin can

also be used for discrete output or its alternate function.

4.2.7 Chip-Select Base Address Registers (CSBARBT, CSBAR[0:10])

Chip-select signals are asserted when the CPU accesses certain ranges of addresses. The base address

registers specify the address ranges for each chip-select circuit.

1. Reprogram the base address and/or blocksize of CSBOOT

if desired. The default value out of reset

is a base address of $000000 with a blocksize of 1 MByte.

2. Program the base address and block size for each chip-select circuit that used. The base address

must be on a word boundary of the block size. For example, for an 8 Kbyte block size, the base ad-

dress can be $2000, $4000, $6000, $8000, etc. If a chip-select circuit is used to generate an interrupt

acknowledge signal or an autovector, the base address register must be set to $FFF8 or higher be-

cause interrupt acknowledge cycles occur in CPU space.

4.2.8 Chip-Select Option Registers (CSORBT and CSOR[0:10])

The option registers control the conditions under which a chip-select signal is asserted.

1. Reprogram the options for CSBOOT if desired. Reducing the number of wait states from the reset

value of 13 increases execution speed.

2. Program the option registers for each chip-select circuit used.

A. MODE — Select asynchronous mode (%0) unless using the ECLK output to provides synchronous

bus timing for 6800 peripherals. In synchronous mode (%1), the STRB and DSACK fields have

no effect.

B. BYTE — This field determines whether to assert the chip-select signal for an upper-byte access,

lower-byte access, both, or neither. When two 8-bit memories are used to make up one16-bit port,

the associated chip-select circuits are programmed identically except for BYTE field values—se-

lect upper byte for one and lower byte for the other.

C. R/W — This field specifies whether to assert the chip-select signal during a read cycle, a write cy-

cle, or both.When the chip-select circuit is used to generate an IACK signal or to provide an au-

tovector, this field must be set to “read.”

D. STRB — This field specifies whether chip-select assertion is synchronous with AS or DS. If a chip-

select circuit is used to generate an IACK signal or to provide an autovector, this field should be

set to “AS.”

E. DSACK — This field either specifies the number of wait states to insert before the chip-select cir-

cuit asserts DSACK and terminates the bus cycle, or it specifies that the external device must pro-

vide the DSACK signal by driving the external DSACK pins. Assertion of the external DSACK pins

will terminate a bus cycle even if the DSACK field is programmed for a certain number of wait