Order this document by MC68332TUT/D MOTOROLA SEMICONDUCTOR DEVICE TUTORIAL An Introduction to the MC68332 By Sharon Darley, Mark Maiolani, and Charles Melear 1 INTRODUCTION Use of microcontrollers (MCUs) presents new challenges as clock speeds increase and bus structures become more complex. In particular, designing a system with Motorola’s 32-bit MC68332 can be challenging for those used to the 8-bit world.
TABLE OF CONTENTS 1 INTRODUCTION ........................................................................................................... 1 2 DESIGNING THE HARDWARE .................................................................................... 3 2.1 Using Data Bus Pins to Configure the MCU ........................................................... 3 2.2 Choosing Memory Width ........................................................................................ 4 2.
2 DESIGNING THE HARDWARE 2.1 Using Data Bus Pins to Configure the MCU The logic level of the data bus pins during reset determines many important operating characteristics of the MCU. Ensuring that the data bus is in a known condition during reset is vital to proper operation because the state of each data bus pin is sampled on the rising edge of the RESET signal.
74HC244s are enabled. Otherwise, if an external RESET signal was applied during a write to external memory and was not conditioned with R/W and DS, the 74HC244s would turn on during the write and cause data bus contention.
Using 8-bit memory simplifies the design and reduces cost, but with a significant performance penalty. This penalty is not fixed, but depends on the amount of time that the processor spends accessing the 8-bit memory as opposed to accessing other external memory or performing internal accesses or operations. Moving from 16-bit to 8-bit program memory may reduce CPU performance by 40% when executing simple CPU instructions that only take a few clock cycles to execute.
Remember that the level 7 interrupt is non-maskable — when configured as an interrupt line, IRQ7 is always enabled. The only way to disable external IRQ7 interrupts is to assign the IRQ7 pin to I/O function via the port F pin assignment register. DSACK[0:1] — During bus transfers, external devices can drive these signals to indicate port width. These signals are active even if the bus transfer is to or from a peripheral that is using one of the chipselects to terminate the bus cycle.
2.5 Clock Circuitry The designer must decide whether to use the internal frequency synthesizer circuit or an external clock to produce the system clock signal. Both options are discussed in the following paragraphs. 2.5.1 Using the Internal Frequency Synthesizer Circuit The MCU uses a voltage-controlled oscillator (VCO) and a phase-locked loop (PLL) to generate an internal high speed clock. This arrangement permits low power operation using only the low frequency oscillator.
NOTE Some older versions of the MC68332 require different components. These mask sets are 1C17P, 1C32J, OC53T, and 1C53T. See Figure 4 for an illustration. C1 22 PF* RS 330KΩ XTAL Rf 10MΩ EXTAL C2 22 PF* VSSI * RESISTANCE AND CAPACITANCE BASED ON A TEST CIRCUIT CONSTRUCTED WITH A DAISHINKU DMX-38 32.768-KHZ CRYSTAL. SPECIFIC COMPONENTS MUST BE BASED ON CRYSTAL TYPE. CONTACT CRYSTAL VENDOR FOR EXACT CIRCUIT. 332TUT XTAL CONN 1 Figure 3 System Clock with a 32.
greater attenuation at the first harmonic. When figuring the reactance of the entire circuit, it is most important to use the typical parameters of the crystal, the input and output capacitance of the amplifier and the remainder of the external components in the calculation. Many companies make crystals. Most re-sell their products through electronics distributors that are listed in the EITD Electronic Industry Telephone Directory.
INTERNAL AMPLIFIER XTAL EXTAL Rf B A 10 MΩ C TO +5 OR GND Rd 332TUT XTAL RF/RD CONN 10 MΩ Figure 5 DC Model of Oscillator Circuit 2.5.2.3 Layout and Strange Behavior Oscillator layout is just as important as a good quality crystal and cleanliness in manufacturing the printed circuit board. The best possible solution is to use a multi-layer board with a separate ground plane. The rules for oscillator layout are quite simple.
2.5.2.4 XFC and VDDSYN Noise on the XFC, VDDSYN, and VSSI pins causes frequency shifts in CLKOUT. The XFC filter capacitor and the VDDSYN bypass capacitors should be kept as close to the XFC and VDDSYN pins as possible, with no digital logic coupling to either XFC or VDDSYN. The ground for the VDDSYN bypass capacitors should be tied directly to the VSSI ground plane. If possible, route VDDSYN and VSSI as separate supply runs or planes.
or, on the other hand, a working oscillator could be moved into a region of no oscillation at all. Therefore, it is important to measure oscillator performance indirectly. This can be done through the CLKOUT pin, which is a buffered form of the internal system clock. Monitoring the CLKOUT pin with an oscilloscope does not affect the oscillator and provides an accurate representation of oscillator problems. If the MCU is running off the internal PLL and a 32.768 kHz crystal, the CLKOUT frequency should be 8.
+5V +5V MC68332 10KΩ 820Ω O.C. RESET 10–100µF +5V LOW VOLTAGE INHIBIT DEVICE 332TUT LVI/RESET CONN Figure 8 Typical MC68332 Reset Circuit When the internal PLL is used to generate the internal system clock, the RESET pin works as follows. At power-up, the MCU drives RESET low. When the PLL locks, the MCU releases RESET for two system clock cycles.
2.7 Power Supply Always connect all power and ground pins to power sources. Since internal power buses only serve about 8 - 10 pins each, the power and ground pins are usually not connected together within the device. If any power pin is left floating, the pins served by the floating power pin can receive power from internal circuitry such as internal protection diodes.
POWER SUPPLY POWER SUPPLY LOW VOLTAGE INHIBIT DEVICE A LOW VOLTAGE INHIBIT DEVICE B 332TUT DUAL RESET CONN Figure 10 Using LVI Devices with Multiple Power Supplies 2.8 Designing for Electromagnetic Compatibility Because of the fast clock speed and relatively short rise and fall times of MCU signals, the designer must consider electromagnetic compatibility (EMC) issues.
VSS TPUCH0 TPUCH1 TPUCH2 TPUCH3 TPUCH4 TPUCH5 TPUCH6 TPUCH7 VSS V DD TPUCH8 TPUCH9 TPUCH10 TPUCH11 VSS V DD TPUCH12 TPUCH13 TPUCH14 TPUCH15 T2CLK VSS V DD ADDR23/CS10 PC6/ADDR22/CS9 PC5/ADDR21/CS8 PC4/ADDR20/CS7 PC3/ADDR19/CS6 PC2/FC2/CS5 PC1/FC1/CS4 PC0/FC0/CS3 VSS 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107
Another way to control power supply noise created by the MCU is to put a small inductor in series with the power supply lines for the port drivers. This method can help control noise on the power traces of the PCB. However, it should be used only as a last resort, because it can introduce other noise problems. Also, a series inductor in the power supply line will probably have little effect on radiated noise, which is generally a result of the port driver switching speed.
• Use ferrite chokes when troubleshooting. Placing a choke around a signal line and the return conductor carrying a differential signal causes fields developed in the ferrite core by the opposing currents to cancel. Ferrite chokes can also be used on input/output lines. Because board-mounted chokes increase the number of holes connecting to the supply planes, they should be used only as a last resort. • Localize any high frequency circuits, such as the clock and address or data buses.
Chip-select access time (MCU read cycle) = (2 + WS) X tCYC(min) - tCLSA(max) - tDICL(min) Chip-select access time (MCU write cycle) = (2 + WS) X tCYC(min) - tCLSA(max) + tCLSN(min) In the equations, WS is the number of wait states programmed in the DSACK field. For fast termination mode, WS = -1, for zero wait states, WS = 0, for one wait state, WS = 1, etc. Also, it is assumed that chipselect assertion is based on address strobe.
2.9.2 Using Chip-Select Signals to Enable Boot Memory The MCU CSBOOT chip-select circuit is always enabled from reset. Because the SRAM module is disabled out of reset, the CSBOOT signal is generally used to select an external boot ROM. The CSBOOT chip-select circuit features hardware-controlled selection of 8-bit or 16-bit bus width. Bus width is controlled by the state of the DATA0 line at the release of the RESET signal.
2.9.3.1 How to Construct Word Memory from Two Byte Memories For chip-select signals other than CSBOOT, forming word memory that is byte-accessible from two bytewide devices is simple. Use a separate chip-select pin for each device, and configure chip-select logic to decode the upper and lower bytes, respectively. Each of the chip-select circuits must be configured as a 16bit port, even though only eight bits of memory are being accessed.
MCU ADDR[16:0] ADDR[13:1] ADDR[13:1] ADDR[16:1] DATA[15:0] DATA[15:8] DATA ADDR WE OE DATA ADDR RAM 32K X 8 RAM 32K X 8 CS0 CS1 CS2 CSBOOT DATA[15:0] DATA[7:0] CE WE OE CE DATA ADDR ROM 32K X 16 CE UPPER BYTE ENABLE LOWER BYTE ENABLE READ ENABLE (BOTH BYTES) ROM ENABLE 332TUT EXT MEM CONN 3 Figure 15 Configuring 16-Bit Memory with 8-Bit RAMs — Separate Read and Write Enables 2.10 Using External Interrupts The MCU has seven external interrupt lines, IRQ[7:1].
2.10.3 Interrupt Vectors Vectors are 32-bit addresses that point to the interrupt service routines (and other exception handlers). They are stored in a data structure called the exception vector table. There are 256 vector addresses in the exception vector table; of these, 199 can be used for interrupts. The base address of the exception vector table is determined by the value stored in the vector base register.
2.10.4.2 Autovectors Autovectors can only be used with external interrupt service requests. When an external device cannot supply a vector number in response to an IACK cycle, an autovector can be used instead.The autovector number is determined by the priority of the interrupt request. For example autovector number 2 corresponds to IRQ2. In order for an autovector to be used the IACK cycle must be terminated by an AVEC signal.
It is very important to make certain that the IRQ7 signal be de-asserted before the level seven interrupt service routine ends. A new level seven interrupt will be recognized in the following cases: If the IRQ7 signal de-asserts and is then re-asserted while the interrupt service routine is executing. If the IRQ7 signal remains asserted until the RTE instruction that ends the service routine is executed.
3 ESTABLISHING COMMUNICATION 3.1 Communicating with the Target Board After a target board has been built, it is generally necessary to communicate with it for debugging purposes. Although a designer can write a ROM monitor or modify CPU32Bug to communicate with the MCU via the serial port, it is simpler and often more effective to use an emulator or the CPU32 background debug mode (BDM) for communication. 3.1.
Table 4 BDM Connections 10-Pin Connector 8-Pin Connector Signal 1 ---- DS Use Data Strobe 2 ---- BERR Output from ICD to BERR input 3 1 GND Ground Reference 4 2 5 3 6 4 FREEZE 7 5 RESET 8 6 IFETCH/DSI 9 7 VDD 10 8 IPIPE/DSO Output from ICD to BKPT input; assertion causes MCU to BKPT/DSCLK first enable and then enter background mode. Once in BDM, this pin becomes the serial clock.
The debugger should now work reliably. That is, programs can be downloaded into the RAM and executed. Alternatively, write the reset vector to memory location $000000. The reset vector is discussed in detail in 4.1.3.1 Initializing the Reset Vector 3.2 Communicating with Motorola Boards Third party vendors sell many types of development tools to help establish communication with the MCU. These tools are described in the Motorola Microcontroller Development Tools Directory.
Press the page up key on the PC keyboard. A small window will open and ask for the character protocol. Select ASCII. Then, when prompted to, type in the name of the S-record file. IBM-PC SERIAL PORT (DB-25) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 EVALUATION BOARD (DB-9) 1 RXD 2 TXD 3 4 GND 5 6 7 8 9 332TUT SERIAL CONN Figure 18 Terminal/PC Cable Diagram for PFB P9 The file transfer is done when the beeper sounds and the underline cursor flashes.
GND GND RESET VDD 1 3 5 7 2 4 6 8 BKPT/DSCLK FREEZE IPIPE1/DSI IPIPE0/DSO 332TUT BERG8 Figure 19 8-Pin BDM Connector 3.2.2 The M68EVS332 The M68332 EVS is exactly the same as the M68EVK332, but has an additional daughter card called the M68DICARD. The user communicates with the DICARD, which in turn communicates with the MCU, with a program called DIBUG (version 1.03 is the latest version). One use for the DICARD is to reprogram the EPROM on the BCC.
4 SYSTEM INITIALIZATION 4.1 Configuring the Central Processing Unit Initial stack pointer and program counter values are fetched from boot ROM. Other CPU resources that must be initialized include the vector base register, the exception vector table, and the CPU status register. 4.1.1 Exceptions An exception is a special condition, such as a reset, an interrupt, or an address error, that pre-empts normal processing.
Table 5 Exception Vector Table Vector Number (Decimal) Vector Offset (Hexadecimal) Assignment 0 0 Reset: Initial Stack Pointer 1 4 Reset: Initial Program Counter 2 - 15 8 - 3C Various Errors and Exceptions 16 - 23 40 - 5C Unassigned, Reserved 24 60 Spurious Interrupt 25 64 Level 1 Interrupt Autovector 26 68 Level 2 Interrupt Autovector 27 6C Level 3 Interrupt Autovector 28 70 Level 4 Interrupt Autovector 29 74 Level 5 Interrupt Autovector 30 78 Level 6 Interrupt Autovector
org DW DW DW DW DW DW DW DW DW DW DW DW $0008 $0000 INT $0000 INT $0000 INT $0000 INT $0000 INT $0000 INT ;put the following code in memory after the reset vector.
2. If using the software watchdog, periodic interrupt timer, or the bus monitor, select action taken when FREEZE is asserted. The freeze software enable (FRZSW) bit determines whether the software watchdog and periodic interrupt timer counters continue to run when FREEZE is asserted, and the freeze bus monitor enable (FRZBM) bit determines whether the bus monitor continues to operate when FREEZE is asserted. 3. Select the interrupt arbitration level for the SIM with the interrupt arbitration (IARB) field.
4.2.5 Periodic Interrupt Control Register (PICR) 1. Determine the appropriate PIT vector number and interrupt priority. 2. Write vector number and interrupt priority to PIV and PIRQL fields in PICR. 4.2.6 Chip-Select Pin Assignment Registers (CSPAR0 and CSPAR1) The chip-select pins can be used in a number of ways. CSPAR determine the functions of the pins. 1. Set up the chip-select pins for discrete output, 8-bit chip-select operation, 16-bit chip-select operation, or alternate function. 2.
states. If a chip-select circuit is used to provide an autovector, fast termination is automatically selected, and the DSACK field is not used. For more information on how to determine the number of wait states needed, see 2.9.1 Using Chip-Selects to Generate DSACK F. SPACE — This field indicates the address space of the access. To access memory, select supervisor/user space. For IACK cycles, select CPU space. G.
MOVE.B CLR.B INITCS: * * * * * * * * * * * * #$7F,(SYNCR).L (SYPCR).L ;set system clock to 16.78 MHz ;disable software watchdog This section initializes two 32K x 8 RAM chips using the Chip Selects. The memory starts at address $30000 and is both byte and word readable and writable. This program assumes that the RAM chips have access times of 85 ns and require no wait states. The DSACK field of the CSOR Registers may need to be adjusted for chips that have faster or slower access times.
4.4 Configuring the Queued Serial Module The queued serial module (QSM) is divided into two submodules: the serial communications interface (SCI) and the queued serial peripheral interface (QSPI). The following sections give basic examples of QSM configuration. See the QSM Reference Manual for more detailed information. 4.4.1 Configuring the SCI The following example program can be assembled with IASM32. It prints a five-character message to the screen. Do the following before running this program: 1.
4.4.2 Configuring the QSPI The QSPI uses a synchronous serial bus to communicate with external peripherals and other MCUs. The QSPI serial protocol is compatible with the serial peripheral interface (SPI) on the M68HC11 and M68HC05 families of MCUs. The module also has a queue, programmable queue pointers that allow up to16 automatic transfers, and a wrap-around mode that allows continuous transfers to and from the queue with no CPU intervention.
;state of SCK as low, capture data on the ;leading edge of SCK, baud rate is 4.19 MHz ;The BITS filed is a don’t-care value because ;the BITSE filed is cleared, thus selecting ;8 data bits per transmission. * * * * * * * The next command sets the control parameters. Interrupts are not enabled. To enable interrupts upon assertion of the SPIF bit, set SPCR2[15]. To clear an interrupt, read and then clear the SPIF bit. Wrap-around mode is enabled. NEWQP is set to zero, and ENDQP is set to $F.
4.5 Configuring the Time Processor Unit The time processor unit (TPU) is an intelligent, semi-autonomous timer that has16 independently-programmable channels. The TPU can run pre-programmed timing functions stored in an internal ROM, or it can run custom functions. Currently, there are two versions of the TPU, differentiated by the type of pre-programmed functions in ROM. The version designated MC68332A has an automotive function set, while the version designated MC68332G has a motion control function set.
4.5.1.2 Channel Function Select Registers Channel function select registers (CFSR[1:3]) contain the function numbers assigned to each individual channel. These function numbers are mask-set dependent because they are determined by the microcode assembly. 4.5.1.3 Host Sequence Registers Host sequence registers (HSQR0 and HSQR1) contain the host sequence bits for the function running on a particular channel. The host sequence bits determine the mode of a particular function.
4.5.2 Parameter RAM Registers Each channel has a dedicated set of word-long registers (called parameters) in the parameter RAM. TPU Channels 0 - 13 have five parameters, and channels 14 and 15 have seven parameters. The CPU and the TPU communicate through the parameter RAM. The meaning of each location in the parameter RAM is defined by the microcode for a particular function. In the TPU manual, addresses in parameter RAM for channels 0 to 13 are defined as $YFFFW0, $YFFFW2, $YFFFW6, $YFFFW8, and $YFFFWA.
4 ∗ $84 + $00 = $210 Thus, the starting address of the interrupt routine must be stored in location $210. 2. Store an interrupt priority level for the TPU in bits 10 through 8 of the TICR. A. This value determines the priority of TPU interrupt service requests. The value must be a number between 1 and 7— level 7 has the highest priority, and level 1 has the lowest. The value stored in the IPL field in the CPU status register determines whether an interrupt request is recognized.
*** Interrupt Initialization on Channel 4 *** MOVE.W OVE.L #$0680,(TICR).l #INT,($0210).l ;Interrupt level = 6, base vector = $80 ;start interrupt routine at label INT ;assuming VBR is equal to zero ;allow interrupts on level 6 and ;above (assume reset condition of SR) NDI.W #$F5FF,SR CLR.L MOVEC ORI.W ORI.W D0 D0,VBR #$0005,(TMCR).l #$0010,(CIER).l ;initialize VBR to zero ;set IARB field to $5 ;enable interrupts for channel 4 #$FFEF,(CISR).
5 TROUBLESHOOTING Because of the complexity of the MCU, there are a considerable number of potential ‘fatal flaws’ that can cause a prototype application to either not operate from power up, or to fail soon after. This section covers common problems, causes, and fixes.This is not an exhaustive discussion, but is intended to be used as a check list of the main problem areas that can cause an application to fail. 5.
2. If the code does disable the watchdog, but the device is still resetting every 16 ms, then the code is probably not being executed. Either the memory is not programmed properly, or something is preventing the MCU from executing code. Check all pull-up resistors for good connections and correct values. Also check the frequency of CLKOUT. 5.2.3 Problem: CLKOUT Frequency is Incorrect 1. MODCLK is not driven correctly during reset.
rupt lines (by writing to the PFPAR register). This problem is likely to be intermittent, as it would only occur if an IRQ7 interrupt is received in the short time before system initialization. See 2.1 Using Data Bus Pins to Configure the MCU. 3. An interrupt is received, and the interrupt vectors have not been initialized. Make sure that the interrupt vectors are initialized. See 4.1.3.2 Initializing Exception Vectors other than Reset. 4.
A. The CPU recognizes the occurrence of a valid interrupt request and begins the IACK cycle. If none of the modules enter arbitration by asserting an IARB field value, the spurious interrupt monitor asserts BERR internally. B. After arbitration, the interrupt source that wins arbitration does not terminate the IACK cycle with DSACK or AVEC. In this case, the bus monitor asserts the internal BERR signal. C. An external device terminates the IACK cycle by asserting BERR.
B. Compare the base address register values to see if any overlap. In addition to checking the actual values in the registers, check the block sizes and thus the number of address lines compared. Since the MCU does not look at all 24 address lines when it compares for a match, two chip-select circuits can respond to the same base address, even though the base address registers contain different values.
6 SOURCES OF INFORMATION 6.1 Technical Literature All Motorola literature can be ordered by mail from Motorola Literature Distribution Centers (shown on the back page of this publication) or through local sales offices. For U.S. and European literature orders, call (800) 441-2447. Motorola publication BR1116/D, Advanced Microcontroller Technical Literature, includes a complete listing of literature, sales offices, distributors, and an order form. 6.1.1 User’s Manual MC68332 User’s Manual (MC68332UM/AD) 6.
TPUPN13/D Stepper Motor TPU Function (SM) TPUPN14/D Position Synchronized Pulse Generator TPU Function (PSP) TPUPN15A/D Period Measurement with Additional Transition (PMA) TPUPN15B/D Period Measurement with Missing Transition TPU Function (PMM) TPUPN16/D Input Transition Capture TPU Function (ITC) TPUPN17/D Pulse Width Modulation TPU Function (PWM) TPUPN18/D Discrete I/O TPU Function (DIO) TPUPN19/D Synchronized Pulse Width Modulation TPU Function (SPWM) TPUPN20/D Quadrature Decode TPU Func
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications.
