User`s manual

FUNCTIONAL DESCRIPTION
M68332BCC/D 4-3 MOTOROLA
REV 1
4.2.1.1 32-Bit Central Processor Unit
The CPU32 is the central processor for the MC68332 MCU device. The CPU32 is source and
object code compatible with the MC68000 and MC68010. All user programs can be executed
unchanged. The CPU32 features are:
• 32-Bit internal data path and arithmetic hardware - 16-bit external data bus
• 32-Bit internal address bus - 24-bit external address bus
• Powerful instruction set
• Eight 32-bit general purpose data registers
• Seven 32-bit general purpose address registers
• Separate user and supervisor stack pointers and address spaces
• Separate program and data address spaces
• Flexible addressing modes
• Full interrupt processing
4.2.1.2 Time Processor Unit
The Time Processor Unit (TPU) optimizes performance of time-related activities. The TPU has a
dedicated execution unit, tri-level prioritized scheduler, data storage RAM, dual time bases, and
microcode ROM which drastically reduces the need for CPU intervention. The TPU controls
sixteen independent, orthogonal channels; each channel has an associated I/O pin and can
perform any time function. Each channel also contains a dedicated event register, for both match
and input capture functions.
Each channel can be synchronized to either of two 16-bit, free-running counters with a pre-scaler.
One counter, based on the system clock, provides resolution of TPU system clock divided by 4.
The second counter, based on an external reference, also provides resolution of TPU system
clock divided by 8. Channels may also be linked together, allowing the user to reference
operations on one channel to the occurrence of a specified action on another channel, providing
inter-task control.
4.2.1.3 Queued Serial Module
The QSM contains two serial ports. The queued serial peripheral interface (QSPI) port provides
easy peripheral expansion or inter-processor communications via a full-duplex, synchronous,
three-line bus: data-in, data-out, and a serial clock. Four programmable peripheral select pins
provide address-ability for as many as 16 peripheral devices. A QSPI enhancement is an added
queue in a small RAM. This lets the QSPI handle as many as 16 serial transfers of 8- to 16-bits
each, or to transmit a stream of data as long as 256 bits without CPU intervention. A special
wrap-around mode lets the user continuously sample a serial peripheral, automatically updating
the QSPI RAM for efficient interfacing to serial peripheral devices (such as analog-to-digital
converters).