Operating instructions
QE
J1nemonic
Arguments
"return,"
it restores the address
of
that
instruction to the
stack
and executes a
real 6502
RTS.
This causes the pro-
cessor to continue execution
of
the
machine code following. Thus, Sweet·16
code and real 6502 code may
be
mixed
together in sequence, with Sweet-16
be-
ing
called
by a JSR
instruction
preceding each
"chunk"
of
Sweet-16
code.
The Sweet-16 processor contains
16
registers, each simulated by two page
zero locations. Register
15
doubles as
the Sweet-16 program counter. As ex-
plained above, the actions
of
the various
Sweet-16
instructions
cause the con-
tents of the virtual
PC
to
be
updated. The
cycle of execution
of
the Sweet-16
machine is:
1.
Fetch Opcode
LDY
#00
LDA
(R15),Y
2.
Execute Opcode
Transfer con-
trol to the ap-
propriate sec-
tion
of
Sweet-16.
3.
Repeat at
1.
or Return to caller (if inter-
pretive opcode was
"return".
The following table briefly sum-
marizes the opcodes which the Sweet-16
machine provides. The mnemonics used
in the table are those chosen for the
macro implementation discussed below.
Further details and some examples may
be found in the November 1977 issue
of
BYTE
magazine.
The Macros: How They
Work
Listing
1.
shows the Sweet-16
macros as defined for the Carl Moser
ASMITED macro assembler. The macros
fall into
two
groups: the register and the
non-register opcodes. The register op-
codes are all assembled
to
values with a
non-zero
($1
to
$F)
high nibble: e.g.
LD@(R12)
-$4C.
The non-register op-
codes all have a 0 value in the high nib-
ble
of
the opcode byte. Most
of
the non-
register opcodes have a second byte
which
indicates
a
relative
branch
Effect
displacement value, in the style
of
the
6502 itself. The most interesting part of
the set of macro definitions involves the
calculation
of
this displacement. Since
the concept of relative branch displace-
ment is common to all the branching
operations, a separate macro is defined
which is used to calculate the displace-
ment. This macro then gets called in the
body
of
each branching opcode to pro-
vide the desired value:
!!!RELBR .MD
(LOC)
f F P =
-LOC
.
BY
LOC-
=-1
IF
M
=-LOC
.
BY
=-LOC+
1
.ME
! !
! B R .MD (WHERE)
.BY
1
RELBR (WHERE)
.ME
Table
1:
Sweet-16
Instruction set
Summary
In
SETR (Rn
,Constant)
2n
LD
(Rn)
3n
ST
(Rn)
4n
LD(~
(Rn)
5n
ST(~
(Rn)
6n
LDD@
(Rn)
7n
STD@
(Rn)
8n
POP@
(Rn)
9n
STP@
(Rn)
An
ADD
(Rn)
Bn
SUB
(Rn)
Cn
POPD@
(Rn)
Dn
CPR
(Rn)
En
INCR
(Rn)
Fn
DECR
(Rn)
00
RTN
01
BR
(addr)
02
BNC
(addr)
03
BC
(addr)
04
BP
(addr)
05
BM
(addr)
06
BZ
(addr)
07
BNZ
(addr)
08
BMI
(addr)
09
BNMI
(addr)
OA
BK
OB
RS
OC
BS
(addr)
Rn
<-
Constant
RO
<-
Rn
Rn
<-
RO
High
byte
of
RO
<-
0
Low
byte
of
RO
<-
(Rn)
(Rn)
<-
Low
byte
of
RO
RO
L
<-
(Rn);
Rn
<-
Rn+l;RO
H
<-
(Rn)
(Rn)<- ROL;Rn
<-
Rn+l;
(Rn)
<-
RO
H
Rn
<-
Rn-l;RO
L
<-
(Rn);RO
H
<-
0
Rn
<-
Rn-l;
(Rn)
<-
ROL;Rn
<-
Rn-l;
(Rn)
<-
RO
H
RO
<-
RO
+ Rn
RO
<-
RO
- Rn
Rn
<-
Rn-l;RO
<-
(Rn);Rn
<-
Rn-l;
RO
H
<-
(Rn)
L
Set
branch
conditions
as
a
result
of
RO
-
Rn.
Store
result
into
R13.
Rn<-Rn+l
Rn<-Rn-l
Return
to
caller
Relative
branch
to
addr.
(Note:
Argument
is
assembled
as
displacement.
Source
argument
is
absolute.)
Branch
if
No
Carry
Branch
if
Carry
Branch
if
prior
result
Plus
Branch
if
prior
result
Minus
Branch
if
prior
result
Zero
Branch
if
prior
result
Non
Zero
Branch
if
prior
result
=
-1
Branch
if
prior
result
f
-1
Execute
6502
Break
instruction
Return
from
Sweet-16
subroutine
Branch
to
Sweet-16
subroutine.
addr
must
be
in
the
range
allowable
for
a
relative
branch.
Return
address
is
stored
in
a
pseudo-stack
whose
address
is
contained
in
R12.
The RELBR macro uses the condi-
tional assembly features
of
the macro
assembler. Let us examine
it
line by line:
!!!RELBR .MD
(LOC)
This line indicates to the assembler
that a Macro Definition is being in-
itiated. The name by which the macro
may subsequently
be
called is RELBR
and the argument which must be sup-
plied when
it
is called is represented by
the dummy symbol
LOC.
When the
macro is expanded by a call, the actual
argument which is supplied in the call
will be substituted for each occurrence
of 'LOC' in the body
of
the definition.
IF
P =
-LOC
This line contains one
of
thecondi-
tional assembly operations or directives
of the assembler: IFP. The assembler is
directed to evaluate the expression con-
tained in the remainder of the line; in
this. case
..
=
-LOC".
If
the result is a
positive number (the mnemonic stands
for
IF
Positive), then the assembler will
assemble all instructions following the
current line until it encounters a line
containing···,
which indicates the end
of
the scope of the IFP directive. If the
expression evaluates to a negative
number or zero, then the assembler will
ignore all instructions following the cur-
rent line until the matching
•••.
The
expression'
=
-LOC'
is com-
puted by subtracting the value of the ac-
tual parameter substituted for
LOC
in
the
call
from
the
value
of
the
assembler's
location
counter,
represented
in
ASM/TED
by
the
January, 1980 MICRO
--
The
6502 Journal
20:27