Order this document by MC68030EC/D MOTOROLA m SEMICONDUCTOR TECHNICAL DATA MC68030 ELECTRICAL SPECIFICATIONS ( • MOTOROLA (~)MOTOROLA INC.
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ELECTRICAL SPECIFICATIONS MAXIMUM RATINGS Symbol Value Unit Supply Voltage* Rating VC~C -0.3 to +7.0 V Input Voltage Vin - (~:5 to + 7.0 "V TA TA 0 70 TC 80 Tstg - 5 5 to 150 Operating Temperature Range Minimum Ambient Temperature 40-MHz Maximum Ambient Temperature 50-MHz Maximum Case Temperature Storage Temperature Range °C °C *A continuous clock must be supplied to the MC68030 when it is powered up.
POWER CONSIDERATIONS The average chip-junction temperature, T j , in °C can be obtained from: T j = T A + (PD ° 03A) (1 where:. .. TA = Ambient Temperature, °C 0jA = Package Thermal Resistance, Junction-to-Ambient, °C/W PD = PINT+ PI/O 'PINT = I c c x V c c , W a t t s - - Chip lnternaI Power PI/O . - Power,Dissipationon Input and Output Pins - - User Determined -. For most applications PI/O
AC ELECTRICAL SPECIFICATIONS DEFINITIONS • The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of the MC68030 clock input and, possibly, relative to one or more other signals. The measurement of the AC specifications is defined by the waveforms in Figure 1. To test the parameters guaranteed by MQtorola, inputs must be driven to the voltage levels •specified in~ Figure 1.
" " ' " ' DRIVE TO 2.4 V CLK D°TPUTS(2):L~ ..... , ........ ' To 2:iv " " T A - - Y - 2.0 v VAL,O 28 v - & V 7 7 ;RIVE IN0T 08V T00,v . t._c4._0_, t INPUTS(4)CLK ALL SIGNALS(S) VAL'O '" ~ 2 " 0 V 2.OV .'VA"0' I 00TP,T° 0 . a V ~ V _ / _ / - ' I ~ _ ~ V OUTPOTo+, "-~2E08; . :NApL~DT: . : : ~ T02.4V V . --~-. ~ - 2.0 V 0.
DC ELECTRICAL SPECIFICATIONS ( V c c = 5.0 Vdc_+ 5%; G ND = 0 Vdc; 40 MHz-T A = 0 ° to 70°C, 50 M Hz-TA = 0°C to T C = 80°C) • .. Characteristic Symbol Min Unit Max Input High Voltage ViH 2.0 VCC Input Low Voltage VIL' GND -0.5 0.8 lin -2.5 2.5 Input Leakage Current GND ~< Vin ~< VCC BERR, BR, BGACK, CEK,,IPL0-1PL2, AVEC ,CDIS, DSACKO, DSACK1 HALT, RESET Hi-Z (Off-State) Leakage Current (, 2.4 V/0.
AC ELECTRICAL SPECIFICATIONS - - READ A N D WRITE CYCLES• ( V c c . = 5.0 V d c - + 5 % ; G N D = 0 (see..Figures.3-8) Vdc; 40 MHz-TA =0 ° to 70°C, 50 MHz-TA =0°.C to TC =80°C) 20MHz Num." 6 C!ock'Hig h to Function Code, Size, R M C , I P E N D , CLOUT, A d d r e s s Valid 6A 6B .33.
A C ELECTRICAL S P E C I F I C A T I O N S (Continued) 20MHz Num. 25MHz " {' 33.33MHz 40MHz 50MHz* Unit Characteristic Min ,Max Min Max Min Max Min Max Min Max 5 -- 3 -- 3 -- ns ns 17' A'--S, D~ Negated to R/W Invalid 1Q --- .7" --~ 18 Clock High to R / ~ High O 25 0 20 0 15 O 14 0 14 20 Clock High to R/W Low 0 25 0 20 O 15 0 !4 O 14 ns 21 R/W'High to A T 'Asserted 10 -- 7 5 -- 5 -- 3 -- ns .
AC ELECTRICAL SPECIFICATIONS '" NUm. .~ 20 MH~' " 33~33 MHz 40 M H z 50 M H z * Unit BGACK Asserted to BG.Negated 37A 6 ,. BG-ACK Asserted to ~ . 25 MHz Characteristic 'Min 37 (Continued) Negated: Max" Min Max Min Max Min Max Min Max 1.5 3.5 1,5 3.5 1.5 3,5 1,5 3.5 1.5 3.5 Clks Clks .0. 1.5 0, 115 0 1.5 0 1.5 0 1.5- 39. BG Width" Negated 75 -- 60 -- 45 -- 30 -- 30 -- ns 39A B'G Width' Asserted 75 -- 60 -- 45 -- 30 -- :30 -- ns @.
AC ELECTRICAL SPECIFICATIONS (Concluded) Num. 20 MHz Characteristic 25 MHz 33.
.-@ Figure 2. Clock Input Timing Diagram . 10 . . . . , , . .
$1 CLK $2 $3 $4 $5 _ _ 2 ~"-2- . _ _ . m AO-A31, FCO.FC2 m SIZ0-SIZI RMC ~-.~ oc-g - - @ ~ ~_ (~- ® ~ (5>. ® ---i ® R/W ® DSACKO OSACKI (~. .- ],. ® 8ERR .@ HALT ALL ASYNCHRONOUS INPUTS CIIN ¥ % % . ' ~'~) Figure 3.
SO SI $2 $3 . $4 $5 SO A0-A31, FC0-FC2 / SIZ0-SIZ1 RMC- . ~_ --~ ® '0-'~ .Z, ---tP @ - . _/ ® 00-031 -.4 ~ --.<~ F.igure:4: Asyncliro'nous Write .Cycle Timing.
SO $1 $2 S3 SO Sl S2 AO-A3!.FC0-FC2 ,,--__% SIZO-SIZ1 - - J • --lID ,).4.-4 8 I - . " , , . .RMC .® - [c-~ - - - ~ , ...@_ i i i,.-- DBEN -@ t" CLOUT , CBREO OSACK0/0SACKI J STERM CIIN CBACK "1 00-031 Figure 5. SynchronousReadCycle Timing Diagram MOTOROLA • • , MC68030 . ELECTRICAL . . . . . . SPECIEICATIONS . . .
SO SI $2 S3 SO Sl S2 CLK A0-A31. FC0-FC2 SIZ0-SlZ~i RMC • A~." ECS m OCS R/W 00.031 OSACK0/DSACKI .___/ .... HAL'--"T 141 .. z ~ r Figure 6. Synchronous Write Cycle Timing Diagram 14 MC68030"EI'ECTRICAL SPECIF.
SO $1 $2 $3 $4 $5 CLK A0-A31 ~ ' < 00-031 FC0-FC2 SIZ0-SIZI EC7~ _ _ _ ~ \ \ R/W DBEN 0SACK0 \ 0SACKI \ ' ® 4: --t_ ® / 86ACK i i I Figure 7.
CLK ~ IPENO MMU01S C01S STATUS REFILL } Figure 8.
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