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and may change only when

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S is deasserted. A0-A31 are three-stated during hard-

ware reset.

D0-D31 (Data Bus) - three-state, active high, bidirectional input/outputs when a bus master or

not a bus master. The Data Enable (

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E) input acts as an output enable control for

D0-D31. As a bus master, the data lines are controlled by the CPU instruction execution

or the DMA controller. D0-D31 are also the Host Interface data lines. If there is no ex-

ternal bus activity, D0-D31 are three-stated. D0-D31 are also three-stated during hard-

ware reset.

S1,S0 (Space Select) - three-state, active low outputs when a bus master, three-stated when

not a bus master. Timing is the same as the address lines A0-A31. S1 and S0 are three-

stated during hardware reset.

These signals can be viewed in different ways, depending on how the external memo-

ries are mapped. They support the trend toward splitting memory spaces among ports

and mapping multiple memory spaces into the same physical memory locations. Sev-

eral examples are given in Figure 2-3 . The encoding S1:S0=11 may be used to place

external memories in their low power standby mode.

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W (Read/Write)- three-state, active low output when a bus master, active low input when

not a bus master. Bus master timing is the same as the DSP96002 address lines, giving

S1 S0 MEMORY SPACE

1 1 No access

1 0 P access

0 1 X access

0 0 Y access

EXTERNAL MEMORY AND MAPPING S1 FUNCTION S0 FUNCTION

P only —

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X only

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S—

Y only

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S—

X and Y mapped as 1 or 2 spaces

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SX/

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P and X mapped as 2 spaces

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P and Y mapped as 1 space

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S and

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P, X, and Y mapped as 1 space

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S—

Figure 2-3. Program and Data Memory Select Encoding