Stereo System User Manual

ManualsBrandsMotorola ManualsStereo SystemDSP96002

831

832

833

834

835

836

837

838

839

840

50 MOTOROLA

Table 4 Internal I/O Memory Map of the X Data Memory Space

ADDRESS REGISTER

$FFFFFFFF IPR - Interrupt Priority Register

$FFFFFFFE BCRA - Port A Bus Control Register

$FFFFFFFD BCRB - Port B Bus Control Register

$FFFFFFFC PSR - Port Select Register

: RESERVED :

$FFFFFFF0 Reserved for OnCE Operation (OGDBR)

$FFFFFFEF HTXA/HRXA - HOSTA HTX/HRX Register

$FFFFFFEE HTXCA - HOSTA HTX Reg. and HMRC Clear

$FFFFFFED HSRA - HOSTA Status Register

$FFFFFFEC HCRA - HOSTA Control Register

: RESERVED :

$FFFFFFE9 TCR1 - Timer Count Register 1

$FFFFFFE8 TCSR1 - Timer Control Status Register 1

$FFFFFFE7 HTXB/HRXB - HOSTB HTX/HRX Register

$FFFFFFE6 HTXCB - HOSTB HTX Reg. and HMRC Clear

$FFFFFFE5 HSRB - HOSTB Status Register

$FFFFFFE4 HCRB - HOSTB Control Register

$FFFFFFE3 RESERVED :

$FFFFFFE2 RESERVED

$FFFFFFE1 TCR0 - Timer Count Register 0

Table 5 Interrupt Vector Addresses

$FFFFFFE0 TCSR0 - Timer Control Status Register 0

$FFFFFFDF DSM0 -DMA CH0 Source Modiﬁer Register

$FFFFFFDE DSR0 -DMA CH0 Source Address Register

$FFFFFFDD DSN0 -DMA CH0 Source Offset Register

$FFFFFFDC DCO0 -DMA CH0 Counter Register

$FFFFFFDB DDM0 -DMA CH0 Destination Modiﬁer Register

$FFFFFFDA DDR0 -DMA CH0 Destination Address Register

$FFFFFFD9 DDN0 -DMA CH0 Destination Offset Register

$FFFFFFD8 DCS0 -DMA CH0 Control/Status Register

$FFFFFFD7 DSM1 -DMA CH1 Source Modiﬁer Register

$FFFFFFD6 DSR1 -DMA CH1 Source Address Register

$FFFFFFD5 DSN1 -DMA CH1 Source Offset Register

$FFFFFFD4 DCO1 -DMA CH1 Counter Register

$FFFFFFD3 DDM1 -DMA CH1 Destination Modiﬁer Register

$FFFFFFD2 DDR1 -DMA CH1 Destination Address Register

$FFFFFFD1 DDN1 -DMA CH1 Destination Offset Register

$FFFFFFD0 DCS0 -DMA CH1 Control/Status Register

$FFFFFFCF RESERVED

: RESERVED :

$FFFFFF80 RESERVED

ADDRESS REGISTER