Stereo System User Manual

6 - 6 DSP96002 USER’S MANUAL MOTOROLA
Bcc Branch Conditionally
BRA Branch Always
BRCLR Branch if Bit Clear
BRSET Branch if Bit Set
BScc Branch to Subroutine Conditionally
BSCLR Branch to Subroutine if Bit Clear
BSR Branch to Subroutine
BSSET Branch to Subroutine if Bit Set
DEBUG Enter Debug Mode
FBcc Branch Conditionally
FBScc Branch to Subroutine Conditionally (Floating-Point Condition)
FFcc Conditional Data ALU Operation without CCR Update
FFcc.U Conditional Data ALU Operation with CCR Update
FJcc Jump Conditionally
FJScc Jump to Subroutine Conditionally
FTRAPcc Conditional Software Interrupt
IFcc Conditional Data ALU Operation without CCR Update
IFcc.U Conditional Data ALU Operation with CCR Update
ILLEGAL Illegal Instruction Interrupt
Jcc Jump Conditionally
JCLR Jump if Bit Clear
JMP Jump
JScc Jump to Subroutine Conditionally
JSCLR Jump to Subroutine if Bit Clear
JSET Jump if Bit Set
JSR Jump to Subroutine
JSSET Jump to Subroutine if Bit Set
NOP No Operation
RESET Reset Peripheral Devices
RTI Return from Interrupt
RTR Return from Subroutine and Restore Status Register
RTS Return from Subroutine
STOP Stop Processing (low power stand-by)
TRAPcc Conditional Software Interrupt
WAIT Wait for Interrupt (low power stand-by)
Figure 6-7. Program Control Instructions
6.3 INSTRUCTION FORMAT
Because of the multiple bus structure and the parallelism of the DSP96002, up to 3 data transfers may be
specified in the instruction word - one on the X Data Bus, one on the Y Data Bus and one within the Data
ALU. A fourth data transfer is generally implied and occurs in the Program Controller (instruction word
fetch, program looping control, etc.). Each data transfer will involve a source and a destination.