Stereo System User Manual

MOTOROLA

2.13 CACHE USE SCENARIO

This section demonstrates a possible scenario of cache use in a real time system.

1. The DSP96002 leaves the hardware reset in PRAM mode as determined by the mode

bits in the OMR.

2. To achieve “hit on ﬁrst access” (especially important for the fast interrupt vectors), the

user, while still in PRAM mode and using DMA, transfers the interrupt vectors and

some critical routines into the lower PRAM addresses. The DMA transfers set the cor-

responding valid-bits. Presume that the code uses 200 PRAM words and therefore it

will be contained in 2 cache sectors. Since these routines are time critical, the user will

wish to lock the sectors. A possible code may look like this:

LABEL ADDRESS CODE

$00000000 reset vector

. . .

$0000003e host b write p memory vector

user_code $00000040 user critical routines

. . .

$0000007f end of sector 1

$00000080 beginning of sector 2

. . .

$000000c8 end of user critical routines

3. To enter cache mode, the user sets OMR bit 4. To lock address 0 to 200 in the cache

the user issues the PLOCK instruction twice, each time with an effective address that

belongs to the corresponding memory sector. Please notice that three cycles should

separate the change of OMR bit 4 from the PLOCK instruction.

The code may look like this:

ORI #$10, OMR ; set CE bit in OMR

NOP ; pipeline delay

PLOCK #0 ; lock sector containing address 0

MOVE #128, R0 ; load effective address to r0

NOP ; pipeline delay for move

PLOCK R0 ; lock sector containing address 128