Stereo System User Manual

MOTOROLA DSP96002 USER’S MANUAL A - 245
FFcc.U Floating-Point iF FFcc.U
Conditional Instruction
with CCR, ER, IER Update
Operation:
If cc, then opcode operation
S → D
Assembler Syntax:
Opcode-Operands S,D FFcc.U
FFcc.U
Description:
If the specified floating-point condition is true, transfer data from the specified source S to the specified
destination D. Also, store result(s) of the specified Data ALU operation and update the CCR, ER and IER
registers with the status information generated by the Data ALU operation. If the specified condition is
false, no destinations are altered and the status register is not affected by the Data ALU operation. The
UNCC bit in the ER register and SIOP flag in the IER are set by the FFcc.U instruction if the NAN bit in the
ER register was set and the specified condition is one of the conditions with a "Yes" entry in the "Set UN-
CC" column. If no register move is specified, this instruction is assembled with a R0 to R0 move.
"cc" may specify the following conditions:
Non-aware
Mnemonic Condition Set UNCC*
EQ - equal Z = 1 No
ERR - error UNCC v SNAN v OPERR v No
OVF v UNF v DZ = 1
GE - greater than or equal NAN v (N & ~Z) = 0 Yes
GL - greater or less than NAN v Z = 0 Yes
GLE - greater, less or equal NAN = 0 Yes
GT - greater than NAN v Z v N = 0 Yes
INF - infinity I = 1 Yes
LE - less than or equal NAN v ~(N v Z) = 0 Yes
LT - less than NAN v Z v ~N = 0 Yes
MI - minus N = 1 No
NE(Q) - not equal Z = 0 No
NGE - not(greater than or equal)NAN v (N & ~Z) = 1 Yes
NGL - not(greater or less than) NAN v Z = 1 Yes
NGLE - not(greater, less or equal)NAN = 1 Yes
NGT - not greater than NAN v Z v N = 1 Yes
NINF - not infinity I = 0 Yes
NLE - not(less than or equal) NAN v ~(N v Z) = 1 Yes
NLT - not less than NAN v Z v ~N = 1 Yes
OR - ordered NAN = 0 No
PL - plus N = 0 No
UN - unordered NAN = 1 No
Note: The operands for the ERR condition are taken from the ER register.
* See description of UNcc bit in Section A.4.
Move Move