Stereo System User Manual

MOTOROLA DSP96002 USER’S MANUAL A - 17
Operands
Data ALU
Dn Data ALU Registers, n= 0-9, SP/SEP/Integer reference as specified by the Data ALU operation.
Dn.S Floating-Point Registers, n= 0-9 (96 bits) SP reference
Dn.D Floating-Point Registers, n= 0-9 (96 bits) DP reference
Dn.L Integer Registers, n= 0-9 (32 bits, Low part of Dn)
Dn.M Integer Registers, n= 0-9 (32 bits, Middle part of Dn)
Dn.H Integer Registers, n= 0-9 (32 bits, High part of Dn)
Dn.ML Long Integer Register, n=0-9 (Dn.M:Dn.L, 64 bits)
Address Generation Unit
Rn Address registers R0 through R7 (32 bits)
Nn Address offset registers N0 through N7 (32 bits)
Mn Address modifier registers M0 through M7 (32 bits)
Program Controller
PC Program counter (32 bits)
MR Mode register (8 bits)
ER Exception register (8 bits)
IER IEEE Exception register (8 bits)
CCR Condition code register (8 bits)
SR Status register (32 bits)
OMR Operating mode register (32 bits)
LA Hardware loop address register (32 bits)
LC Hardware loop counter (32 bits)
SP System stack pointer (32 bits)
SS System stack RAM (15 x 64 bits)
SSH Upper 32 bits of the contents of the current top of stack.
SSL Lower 32 bits of the contents of the current top of stack.
Addresses
ea Effective address
xxxx Absolute address (32 bits)
xx Short jump address (15 bits sign extended)
pp I/O short address (7 bits one extended)
aa Absolute short address (7 bits zero extended)
<...> The contents of the specified address
X: X memory reference (32 bits)
Y: Y memory reference (32 bits)
L: Long memory reference - X concatenated with Y (64 bits)
P: Program memory reference (32 bits)
Figure A-6. Instruction Description Notation