Technical information

4 Porting and Optimizing DSP56800 Applications to DSP56800E 
Another case is when the (Rn) addressing mode is used and an LEA instruction updates the address
register. As expected, the AGU overflows on the DSP56800. When the code is ported to DSP56800E, the
results are different than in the preceding case. This addressing mode, which exists in the enhanced core to
ensure DSP56800 compatibility, causes the AGU to produce 16-bit addresses by filling the upper 8 bits
with 0, simulating an overflow. If the array is accessed with the sequence shown in Code Example 1, the
next address will be forced to 16 bits, which is an error since the rest of the array is placed above 64K.
Code Example 1. Updating an Address Register (AGU Overflow or Underflow)
; accessing an array
move y0,x:(r2) ; writing Y0 at the address from R2
. . .
; other code that might use the address from R2 register
. . .
lea (r2)+n ; updating the R2 register with the increment from N
; the result is a 16-bit address on both architectures
The solution in this case is to replace the LEA instruction with ADDA, resulting in a 24-bit address.
However, there is no guaranteed method to detect these errors. Memory files can only give indications
about data that might cause problems. Only a careful inspection of the code can reveal incompatibilities.
The code chosen as the main example in this application note had no problems caused by AGU overflow or
underflow.
2.1.2.2 MAC Output Limiter
Be careful with applications that enable the MAC output limiter (by setting the SA bit in the OMR). There
are three instructions—ADC, SBC, and DIV—that are not affected by the state of the SA bit on the
DSP56800E architecture but are affected on the DSP56800. When the DIV, ADC, or SBC instructions are
executed, the accumulator extension registers must contain only sign extension, not significant bits.
Consider how the SA bit affects an ADC instruction on the DSP56800. The arithmetic instruction could be
executed on a whole 36-bit accumulator, returning the correct 36-bit result when the SA bit is 0 or a 32-bit
result when the SA bit is set. This feature was introduced so that the algorithms keep bit exactness on the
DSP56800 (as compared to other DSPs that do not support high-precision arithmetic using extension bits).
The MAC output limiter converts a 36-bit number to a 32-bit number. If it is a positive number and larger
than the maximum value represented on 32 bits, it will be limited at $07FFFFFFF; if it is a negative
number that cannot be represented on 32 bits, it will be limited at $F80000000. On the DSP56800E, the SA
bit does not affect an ADC instruction; the result has 36 bits.
Due to this effect, DSP56800 code that uses the MAC output limiter feature and that includes ADC, DIV,
and SBC instructions that are affected by it should be rewritten so that these instructions are used only with
32-bit sign-extended accumulators. Code Example 2 illustrates the consequence of not following this
recommendation.
Code Example 2. Using ADC with Non-Signed Operands (Different Results)
; example of the effect of the SA bit from OMR
bfset #$10,omr ; setting SA bit
move #$1000,y1
move #$F000,a1 ; no sign extension in A register
adc y,a
; y1= $1000 y0= $0000
; a2= $0 a1= $f000 a0= $0000 <= prior execution
; y1= $1000 y0= $0000
; a2= $0 a1= $7fff a0= $ffff <= execution on DSP56800: limitation occurs
; y1= $1000 y0= $0000
; a2= $1 a1= $0000 a0= $0000 <= execution on DSP56800E: no limitation
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