Technical information

22 Porting and Optimizing DSP56800 Applications to DSP56800E 
Between instruction n2 and n1 is a data ALU pipeline dependency. Because the result becomes available in
B after the Execute 2 phase, the n2 instruction must stall 1 cycle to be able to write the B content in the
memory. Four cycles are needed for execution of the sequence and can be rewritten as shown in
Code Example 32.
Code Example 32. Removing Data ALU Pipeline Dependency
n1: macr x0,y0,b a,x:(r3)+ ; the result b available after Ex2
n2’:move x:(r3),a ; B is not used in this instruction,
; the dependency was removed
n3’:move b,x:(r2)+
; 3 cycles / 3 words
The data ALU pipeline dependency was removed. The core does not stall, thus the sequence is executed in
three cycles instead of four.
Considering that data ALU pipeline dependencies occur most frequently in ported applications, identifying
the code with data ALU dependencies and avoiding this code increases execution speed. To identify the
pipeline dependencies, the programmer must fully understand the structure and behavior of the pipeline,
and must give special attention when writing new code sequences.
5.2 AGU Pipeline Dependencies
The types of AGU pipeline dependencies on the DSP56800E represent almost all AGU dependencies that
occur on the DSP56800, however the behaviors of the two cores differ for a similar dependency. When one
of the conditions presented below occurs on DSP56800E, hardware interlocks are generated and the core
automatically stalls the pipeline 1 or 2 cycles. The stalls can be avoided by introducing one 2-cycle
instruction or two 1-cycle instructions after the instruction that generates an AGU dependency. On
DSP56800 a single instruction is needed to remove an AGU dependency.
A dependency occurs if the same register is used within the next two instructions cycles that immediately
follow and if the register is:
• Used as a pointer in an addressing mode
• Used as an offset in an addressing mode
• Used as an operand in an AGU calculation
• Used in a TFRA instruction.
Consideration must be given to dependencies caused by the modification of the N3 or M01 registers by a
move or bit-manipulation instruction because the core does not automatically stall the pipeline in these
cases. Additionally, a bit-manipulation operation performed on the N register does not automatically stall
the pipeline.
There are some special cases where there are no AGU dependencies. For instance, there is no dependency
when immediate values are written to the address pointer registers, R0–R5, N, and SP. Similarly, there are
no dependencies when a register is loaded with a TFRA instruction. DSP56800 has more restrictions
regarding the AGU pipeline dependencies than does DSP56800E.
There can be situations when a sequence, which did not have dependencies on DSP56800, introduces one
stall on DSP56800E (the reason was explained at the beginning of this subsection). Code Example 33
taken from function tx_sbit (file tx_enc.asm) presents a situation of this type.
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