Technical information

Data ALU Pipeline Dependencies
 Pipeline Effects on DSP56800E 21
not occur on DSP56800 (specifically, data ALU pipeline dependencies and hardware looping
dependencies). Also, DSP56800E eliminated additional dependencies, such as, loading an address register
with an immediate value and using it to address the next immediate instruction.
The DSP56800E core handles the pipeline dependencies in two different manners:
• In most cases a hardware interlock automatically causes stalls of the DSP56800E pipeline. The
assembler can warn the programmer about these cases.
• There are a few cases when the core does not stall (for example, modification of N3 or M01 and
using them to address in the next immediate instruction or hardware looping dependencies). The
assembler can insert NOPs and warn the programmer about this insertion, or it can report an error.
Because of the new types of pipeline dependencies, the code ported from DSP56800 can stall in some
cases. There are examples of data ALU or AGU pipeline effects on DSP56800E in the V.22 bis code. The
DSP core automatically inserts stalls in these cases and the code executes correctly. However, many cycles
are lost during these stalls, so the dependencies that generate them should be removed.
Special attention must be made to dependencies that involve hardware looping. Generally, the ported code
could contain these new types of dependencies, which were not an issue for DSP56800. In the selected
application example these dependencies are not met.
It is assumed that readers are familiar with Chapter 10, “Instruction Pipeline” from the Core Reference
Manual. Several pipeline dependencies and methods to avoid them are illustrated in the selected code.
5.1 Data ALU Pipeline Dependencies
Because of the pipeline structure of DSP56800E, a few pipeline dependencies can occur for data ALU
instructions, dependencies that did not occur on DSP56800. The reason they occur is that the “Execute”
stage in the DSP56800 was broken into four stages in the DSP56800E pipeline; Address Generation,
Operand Prefetch 2, Execute and Operand Fetch, and Execute 2.
The data ALU of DSP56800E can cause pipeline dependencies, when one of the three following
conditions occurs:
• The result of a data ALU instruction executed in the “Late” state (Execute 2) is used in the
instruction that immediately follows as a source register in a move instruction.
• The result of a data ALU instruction executed in the “Late” state is used in the two-stage instruction
that immediately follows as a source register to a multiplication or multi-bit shifting operation. A
dependency does not occur if the result is used in an accumulation, arithmetic, or logic operation in
the instruction that immediately follows.
• An instruction requiring condition codes, such as Bcc, is executed immediately after a data ALU
instruction is executed in the “Late” state.
When a data ALU dependency occurs, core interlocking hardware automatically stalls the core for 1 cycle
to remove the dependency, affecting the execution time of a sequence of instructions, but not the
correctness of the results.
Data ALU pipeline dependencies occur in many code sequences in the ported V.22 bis application.
Although they do not affect the correctness, they introduce extra stall cycles. Code Example 31 is taken
from function RXEQUD (file rx_equpd.asm).
Code Example 31. Data ALU Pipeline Dependency in DSP56800E Ported Code
n1: macr x0,y0,b a,x:(r3)+ ; the result B available after Ex2
n2: move b,x:(r2)+ ; data ALU pipeline dependency
n3: move x:(r3),a ;
; 4 cycles / 3 words
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